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At least 613 records · Page 34

Video Guidance Sensor: Optical Performance Predictions and Results from STS-95 Experiment

The Video Guidance Sensor is a key component of NASA's Automated Rendezvous & Capture Program. The Video Guidance Sensor Uses laser illumination of a passive target in the field of view of an on-board camera and signal processor to determine the relative position and attitude between the target and sensor. The Video Guidance Sensor flew on space shuttle mission STS-95 in November of 1998 and was a marked success. Comparisons of experimental results from that mission and theoretical models predicting the optical performance will be discussed.

Jackson, John L.↗

13kW Advanced Electric Propulsion Flight System Development and Qualification

The next phase of robotic and human deep space exploration missions requires high performance, high power solar electric propulsion systems for large-scale science missions and cargo transportation. Aerojet Rocketdyne's Advanced Electric Propulsion System (AEPS) program is completing development and qualification of a 13kW flight EP system to support NASA exploration. The first use of the AEPS is planned for the NASA Power & Propulsion Element, which is the first element of NASA's cis-lunar Gateway. The flight AEPS system includes a magnetically shielded long-life Hall thruster, power processing unit (PPU), and xenon flow controller (XFC). The Hall thruster, originally developed and demonstrated by NASA's Glenn Research Center and the Jet Propulsion Laboratory, operates at input powers up to 13.3kW while providing a specific impulse over 2600s at an input voltage of 600V. The power processor is designed to accommodate an input voltage range of 95 to 140V, consistent with operation beyond the orbit of Mars. The integrated system is continuously throttleable between 3 and 13.3kW. The program has completed testing of the Technology Development Units and is progressing into the Engineering Development Unit test phase and the final design phase to Critical Design Review (CDR). This paper will present the high power AEPS system capabilities, overall program and design status and the latest test results for the 13kW flight system development as well as the plans for the development and qualification effort of the EP string.

in-space propulsion↗

13kW Advanced Electric Propulsion Flight System Development and Qualification

The next phase of robotic and human deep space exploration missions requires high performance, high power solar electric propulsion systems for large-scale science missions and cargo transportation. Aerojet Rocketdyne's Advanced Electric Propulsion System (AEPS) program is completing development and qualification of a 13kW flight EP system to support NASA exploration. The first use of the AEPS is planned for the NASA Power & Propulsion Element, which is the first element of NASA's cis-lunar Gateway. The flight AEPS system includes a magnetically shielded long-life Hall thruster, power processing unit (PPU), and xenon flow controller (XFC). The Hall thruster, originally developed and demonstrated by NASA's Glenn Research Center and the Jet Propulsion Laboratory, operates at input powers up to 13.3kW while providing a specific impulse over 2600s at an input voltage of 600V. The power processor is designed to accommodate an input voltage range of 95 to 140V, consistent with operation beyond the orbit of Mars. The integrated system is continuously throttleable between 3 and 13.3kW. The program has completed testing of the Technology Development Units and is progressing into the Engineering Development Unit test phase and the final design phase to Critical Design Review (CDR). This paper will present the high power AEPS system capabilities, overall program and design status and the latest test results for the 13kW flight system development as well as the plans for the development and qualification effort of the EP string.

in-space propulsion↗

Field-Programmable Gate Array Computer in Structural Analysis: An Initial Exploration

This paper reports on an initial assessment of using a Field-Programmable Gate Array (FPGA) computational device as a new tool for solving structural mechanics problems. A FPGA is an assemblage of binary gates arranged in logical blocks that are interconnected via software in a manner dependent on the algorithm being implemented and can be reprogrammed thousands of times per second. In effect, this creates a computer specialized for the problem that automatically exploits all the potential for parallel computing intrinsic in an algorithm. This inherent parallelism is the most important feature of the FPGA computational environment. It is therefore important that if a problem offers a choice of different solution algorithms, an algorithm of a higher degree of inherent parallelism should be selected. It is found that in structural analysis, an 'analog computer' style of programming, which solves problems by direct simulation of the terms in the governing differential equations, yields a more favorable solution algorithm than current solution methods. This style of programming is facilitated by a 'drag-and-drop' graphic programming language that is supplied with the particular type of FPGA computer reported in this paper. Simple examples in structural dynamics and statics illustrate the solution approach used. The FPGA system also allows linear scalability in computing capability. As the problem grows, the number of FPGA chips can be increased with no loss of computing efficiency due to data flow or algorithmic latency that occurs when a single problem is distributed among many conventional processors that operate in parallel. This initial assessment finds the FPGA hardware and software to be in their infancy in regard to the user conveniences; however, they have enormous potential for shrinking the elapsed time of structural analysis solutions if programmed with algorithms that exhibit inherent parallelism and linear scalability. This potential warrants further development of FPGA-tailored algorithms for structural analysis.

Singleterry, Robert C., Jr.↗

The onboard processor on OAO-3

The onboard data processor for OAO 3 flight applications executes instructions at the rate of 2 1/2 billion per day. The computer commands, processes data, and controls telemetry subsystem programs onboard the spacecraft.

Taylor, T. D.↗

The development of an engineering computer graphics laboratory

Hardware and software systems developed to further research and education in interactive computer graphics were described, as well as several of the ongoing application-oriented projects, educational graphics programs, and graduate research projects. The software system consists of a FORTRAN 4 subroutine package, in conjunction with a PDP 11/40 minicomputer as the primary computation processor and the Imlac PDS-1 as an intelligent display processor. The package comprises a comprehensive set of graphics routines for dynamic, structured two-dimensional display manipulation, and numerous routines to handle a variety of input devices at the Imlac.

Anderson, D. C.↗

User's guide for CCT2WA (converting CCT's to work-addressable file)

The CCT2WA program, developed to convert the shuttle post-flight computer compatible tape data to a word addressable mass storage file, is described. The use of utility processors that can be used to copy word addressable files from mass storage to mass storage is also described.

Williams, S. D.↗

Federal Aviation Administration weather program to improve aviation safety

The implementation of the National Airspace System (NAS) will improve safety services to aviation. These services include collision avoidance, improved landing systems and better weather data acquisition and dissemination. The program to improve the quality of weather information includes the following: Radar Remote Weather Display System; Flight Service Automation System; Automatic Weather Observation System; Center Weather Processor, and Next Generation Weather Radar Development.

Robert W. Wedan↗

The GPRIME approach to finite element modeling

GPRIME, an interactive modeling system, runs on the CDC 6000 computers and the DEC VAX 11/780 minicomputer. This system includes three components: (1) GPRIME, a user friendly geometric language and a processor to translate that language into geometric entities, (2) GGEN, an interactive data generator for 2-D models; and (3) SOLIDGEN, a 3-D solid modeling program. Each component has a computer user interface of an extensive command set. All of these programs make use of a comprehensive B-spline mathematics subroutine library, which can be used for a wide variety of interpolation problems and other geometric calculations. Many other user aids, such as automatic saving of the geometric and finite element data bases and hidden line removal, are available. This interactive finite element modeling capability can produce a complete finite element model, producing an output file of grid and element data.

Wallace, D. R.↗

The 2nd Symposium on the Frontiers of Massively Parallel Computations

Programming languages, computer graphics, neural networks, massively parallel computers, SIMD architecture, algorithms, digital terrain models, sort computation, simulation of charged particle transport on the massively parallel processor and image processing are among the topics discussed.

Mills, Ronnie↗

Merlin - Massively parallel heterogeneous computing

Hardware and software for Merlin, a new kind of massively parallel computing system, are described. Eight computers are linked as a 300-MIPS prototype to develop system software for a larger Merlin network with 16 to 64 nodes, totaling 600 to 3000 MIPS. These working prototypes help refine a mapped reflective memory technique that offers a new, very general way of linking many types of computer to form supercomputers. Processors share data selectively and rapidly on a word-by-word basis. Fast firmware virtual circuits are reconfigured to match topological needs of individual application programs. Merlin's low-latency memory-sharing interfaces solve many problems in the design of high-performance computing systems. The Merlin prototypes are intended to run parallel programs for scientific applications and to determine hardware and software needs for a future Teraflops Merlin network.

Wittie, Larry↗

Vienna FORTRAN: A FORTRAN language extension for distributed memory multiprocessors

Exploiting the performance potential of distributed memory machines requires a careful distribution of data across the processors. Vienna FORTRAN is a language extension of FORTRAN which provides the user with a wide range of facilities for such mapping of data structures. However, programs in Vienna FORTRAN are written using global data references. Thus, the user has the advantage of a shared memory programming paradigm while explicitly controlling the placement of data. The basic features of Vienna FORTRAN are presented along with a set of examples illustrating the use of these features.

Chapman, Barbara↗

Parallel solver for trajectory optimization search directions

A key algorithmic element of a real-time trajectory optimization hardware/software implementation is presented, the search step solver. This is one piece of an algorithm whose overall goal is to make nonlinear trajectory optimization fast enough to provide real-time commands during guidance of a vehicle such as an aeromaneuvering orbiter or the National Aerospace Plane. Many methods of nonlinear programming require the solution of a quadratic program (QP) at each iteration to determine the search step. In the trajectory optimization case, the QP has a special dynamic programming structure. The algorithm exploits this special structure with a divide- and conquer type of parallel implementation. The algorithm solves a (p.N)-stage problem on N processors in O(p + log2 N) operations. The algorithm yields a factor of 8 speed-up over the fastest known serial algorithm when solving a 1024-stage test problem on 32 processors.

Psiaki, M. L.↗

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Long, Jason D.↗

An overview of flight computer technologies for future NASA

In this paper, we present an overview of current developments by several US Government Agencies and associated programs, towards high-performance single board computers for use in space. Three separate projects will be described; two that are based on the Power PC processor, and one based on the Pentium processor.

space exploration flight computers↗

Parallel Computation of the Jacobian Matrix for Nonlinear Equation Solvers Using MATLAB

Demonstrating speedup for parallel code on a multicore shared memory PC can be challenging in MATLAB due to underlying parallel operations that are often opaque to the user. This can limit potential for improvement of serial code even for the so-called embarrassingly parallel applications. One such application is the computation of the Jacobian matrix inherent to most nonlinear equation solvers. Computation of this matrix represents the primary bottleneck in nonlinear solver speed such that commercial finite element (FE) and multi-body-dynamic (MBD) codes attempt to minimize computations. A timing study using MATLAB's Parallel Computing Toolbox was performed for numerical computation of the Jacobian. Several approaches for implementing parallel code were investigated while only the single program multiple data (spmd) method using composite objects provided positive results. Parallel code speedup is demonstrated but the goal of linear speedup through the addition of processors was not achieved due to PC architecture.

Rose, Geoffrey K.↗

Performance and Application of Parallel OVERFLOW Codes on Distributed and Shared Memory Platforms

The presentation discusses recent studies on the performance of the two parallel versions of the aerodynamics CFD code, OVERFLOW_MPI and _MLP. Developed at NASA Ames, the serial version, OVERFLOW, is a multidimensional Navier-Stokes flow solver based on overset (Chimera) grid technology. The code has recently been parallelized in two ways. One is based on the explicit message-passing interface (MPI) across processors and uses the _MPI communication package. This approach is primarily suited for distributed memory systems and workstation clusters. The second, termed the multi-level parallel (MLP) method, is simple and uses shared memory for all communications. The _MLP code is suitable on distributed-shared memory systems. For both methods, the message passing takes place across the processors or processes at the advancement of each time step. This procedure is, in effect, the Chimera boundary conditions update, which is done in an explicit "Jacobi" style. In contrast, the update in the serial code is done in more of the "Gauss-Sidel" fashion. The programming efforts for the _MPI code is more complicated than for the _MLP code; the former requires modification of the outer and some inner shells of the serial code, whereas the latter focuses only on the outer shell of the code. The _MPI version offers a great deal of flexibility in distributing grid zones across a specified number of processors in order to achieve load balancing. The approach is capable of partitioning zones across multiple processors or sending each zone and/or cluster of several zones into a single processor. The message passing across the processors consists of Chimera boundary and/or an overlap of "halo" boundary points for each partitioned zone. The MLP version is a new coarse-grain parallel concept at the zonal and intra-zonal levels. A grouping strategy is used to distribute zones into several groups forming sub-processes which will run in parallel. The total volume of grid points in each group are approximately balanced. A proper number of threads are initially allocated to each group, and in subsequent iterations during the run-time, the number of threads are adjusted to achieve load balancing across the processes. Each process exploits the multitasking directives already established in Overflow.

Djomehri, M. Jahed↗