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VAX Floating Point to Host Floating Point Conversion (VAXFC) software converts non-ASCII files to unformatted floating-point representation of UNIX machine. This is done by reading bytes bit by bit, converting them to floating-point numbers, then writing results to another file. Useful when data files created by VAX computer must be used on other machines. Written in C language.
CVERT computer program converts AIRSAR data to SIR-C format, or converts SIR-C data to AIRSAR format. Spaceborne Image Radar-C (SIR-C) successfully images areas at many sites around world. SIRC CEOS-READER software package (NPO-19463, NPO-19543) required for reading CEOS headers and decompressing SIR-C data. Written in FORTRAN 77.
As space direct current (dc) power systems continue to grow in size, switching power converters are playing an ever larger role in power conditioning and control. When designing a large dc system using power converters of this type, special attention must be placed on the electrical stability of the system and of the individual loads on the system. In the design of the electric power system (EPS) of the International Space Station (ISS), the National Aeronautics and Space Administration (NASA) and its contractor team led by Boeing Defense & Space Group has placed a great deal of emphasis on designing for system and load stability. To achieve this goal, the team has expended considerable effort deriving a dear concept on defining system stability in both a general sense and specifically with respect to the space station. The ISS power system presents numerous challenges with respect to system stability, such as high power, complex sources and undefined loads. To complicate these issues, source and load components have been designed in parallel by three major subcontractors (Boeing, Rocketdyne, and McDonnell Douglas) with interfaces to both sources and loads being designed in different countries (Russia, Japan, Canada, Europe, etc.). These issues, coupled with the program goal of limiting costs, have proven a significant challenge to the program. As a result, the program has derived an impedance specification approach for system stability. This approach is based on the significant relationship between source and load impedances and the effect of this relationship on system stability. This approach is limited in its applicability by the theoretical and practical limits on component designs as presented by each system segment. As a result, the overall approach to system stability implemented by the ISS program consists of specific hardware requirements coupled with extensive system analysis and hardware testing. Following this approach, the ISS program plans to begin construction of the world's largest orbiting power system in 1997.
As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.
Eight In(Al)GaAs P/N junctions grown epitaxially on a semi-insulating wafer were monolithically integrated in series to boost the approx. 0.4 V photovoltage per typical In(Al)GaAs junction to over 3 volts for the 1 sq cm laser power converter (LPC) chip. This is the first report of a multijunction LPC for the 1.3 to 1.5 microns wavelength range. This wavelength range is optimum for laser power transmission over low- loss single-mode silica optical fiber, and is also useful with high efficiency 1.315 microns iodine lasers in free-space power transmission. Advantages of multijunction LPC designs include the need for less circuitry for power reconditioning and the potential for lower I(exp 2)R power loss. As an example, these LPCs have a responsivity of approx.1 amp/watt. With a single junction LPC, 100 watts/sq cm incident power would lead to about 100 A/sq cM short-circuit current at approx. 0.4 V open-circuit voltage. One disadvantage is the large current would lead to a large 1(exp 2)R loss which would lower the fill factor so that 40 wattS/sq cm output would not be obtained. Another is that few circuits are designed to work at 0.4 volts, so DC-DC power conversion circuitry would be necessary to raise the voltage to a reasonable level. The multijunction LPC being developed in this program is a step toward solving these problems. In the above example, an eight-junction LPC would have eight times the voltage, approx. 3 V, so that DC-DC power conversion may not be needed in many instances. In addition, the multijunction LPC would have 1/8 the current of a single-junction LPC, for only 1/64 the 1(exp 2)R loss if the series resistance is the same. Working monolithic multijunction laser power converters (LPCs) were made in two different compositions of the ln(x)Al(y)Ga(l-x-y)As semiconductor alloy, In(0.53)Ga(0.47)As (0.74 eV) and In(0.5)Al(0.1)Ga(0.4)As (0.87 eV). The final 0.8 sq cm LPCs had output voltages of about 3 volts and output currents up to about one-half amp. Maximum 1.3 microns power conversion efficiencies were approx. 22%. One key advantage of multijunction LPCs is that they have higher output voltages, so that less DC-DC power conversion circuitry is needed in applications.
The low temperature operation of a 48 W, 50 kHz, 36/12 V pulse width modulated (PWM) buck de-de power converter designed with standard commercially available components and devices is reported. The efficiency of the converter increased from 85.6% at room temperature (300 K) to 92.0% at liquid nitrogen temperature (77 K). The variation of power MOSFET, diode rectifier, and output filter inductor loss with temperature is discussed. Relevant current, voltage. and power waveforms are also included.
The goal of this project was to establish the feasibility of a high-voltage DC-DC converter based on a rod-array triggered vacuum switch (RATVS) for the Space Solar Power system. The RATVS has many advantages over silicon and silicon-carbide devices. The RATVS is attractive for this application because it is a high-voltage device that has already been demonstrated at currents in excess of the requirement for an SSP device and at much higher per-device voltages than existing or near-term solid state switching devices. The RATVS packs a much higher specific power rating than any solid-state device and it is likely to be more tolerant of its surroundings in space. In addition, pursuit of an RATVS-based system would provide NASA with a nearer-term and less expensive power converter option for the SSP.
A digital Nonlinear Proportional-Integral-Derivative (NPID) control algorithm was proposed to control a 1-kW, PWM, DC/DC, switching power converter. The NPID methodology is introduced and a practical hardware control solution is obtained. The design of the controller was completed using Matlab (trademark) Simulink, while the hardware-in-the-loop testing was performed using both the dSPACE (trademark) rapid prototyping system, and a stand-alone Texas Instruments (trademark) Digital Signal Processor (DSP)-based system. The final Nonlinear digital control algorithm was implemented and tested using the ED408043-1 Westinghouse DC-DC switching power converter. The NPID test results are discussed and compared to the results of a standard Proportional-Integral (PI) controller.
The feasibility of targeting prolidase as a peptide prodrug-converting enzyme has been examined. The enzymatic hydrolysis by prolidase of substrates for the peptide transporter L-alpha-methyldopa-pro and several dipeptide analogues without an N-terminal alpha-amino group (phenylpropionylproline, phenylacetylproline, N-benzoylproline, and N-acetylproline) was investigated. The Michaelis-Menten parameters Km and Vmax for L-alpha-methyldopa-pro are 0.09 +/- 0.02 mM and 3.98 +/- 0.25 mumol/min/mg protein, respectively. However, no hydrolysis of the dipeptide analogues without an N-terminal alpha-amino group is observed, suggesting that an N-terminal alpha-amino group is required for prolidase activity. These results demonstrate that prolidase may serve as a prodrug-converting enzyme for the dipeptide-type prodrugs, utilizing the peptide carrier for transport of prodrugs into the mucosal cells and prolidase, a cytosolic enzyme, to release the drug. However, a free alpha-amino group appears to be necessary for prolidase hydrolysis.
Contents include the following: 1. NASA mission outlook. 2. Issues with DC/DC converter for space. 3. Statement of newly initiated engineering activities for DC/DC converter. 4. Overview of prototyping work with novel materials. 5. Results of cryogenic testing.
The NASA Glenn Research Center and the Cleveland State University have developed a digitally controlled dc-dc converter to research the benefits of flexible, digital control on power electronics and systems. Initial research and testing has shown that conventional dc-dc converters can benefit from improved performance by using digital-signal processors and nonlinear control algorithms.
The converter produces a linear analog signal that is linearly proportional to a shaft angle of a resolver over 360.degree.. An excitation cosine signal supplied to the resolver and a response cosine signal received from the output windings of the resolver are converted to logic level signals. Digital logic is performed on the logic level signals in a programmable digital logic device to produce a logic level pulse-width modulated signal. The logic level pulse-width modulated signal is used to control a switch to switch between two reference voltage levels to produce a pulse-width modulated signal, which is filtered and buffered to produce the linear analog signal.
An improved subranging or comparator circuit is provided for an analog-to-digital converter. As a subranging circuit, the circuit produces a residual signal representing the difference between an analog input signal and an analog of a digital representation. This is achieved by subdividing the digital representation into two or more parts and subtracting from the analog input signal analogs of each of the individual digital portions. In another aspect of the present invention, the subranging circuit comprises two sets of differential input pairs in which the transconductance of one differential input pair is scaled relative to the transconductance of the other differential input pair. As a consequence, the same resistor string may be used for two different digital-to-analog converters of the subranging circuit.
An indium phosphide photovoltaic cell is provided where one or more quantum wells are introduced between the conventional p-conductivity and n-conductivity indium phosphide layer. The approach allows the cell to convert the light over a wider range of wavelengths than a conventional single junction cell and in particular convert efficiently transparency losses of the indium phosphide conventional cell. The approach hence may be used to increase the cell current output. A method of fabrication of photovoltaic devices is provided where ternary InAsP and InGaAs alloys are used as well material in the quantum well region and results in an increase of the cell current output.
A CCD parallel-to-serial converter comprising two successions of charge transfer stages, recurrently side-loaded with respective ones of parallelly supplied charge packets, then serially unloaded by time-interleaved respective shift register operations. The charge packets converted to time-division-multiplexed serial form are supplied to a shared electrometer, and the electrometer response is de-multiplexed. Preferably, shift register operations are carried forward concurrently at the same rate, but with the final charge transfer stages clocked in phases staggered in time.
A process for converting in depth a carbon or graphite preform object to a silicon carbide object, silicon carbide/silicon object, silicon carbide/carbon-core object, or a silicon carbide/silicon/carbon-core object, by contacting it with silicon liquid and vapor over various lengths of contact time in a reaction chamber. In the process, a stream comprised of a silicon-containing precursor material in gaseous phase below the decomposition temperature of said gas and a coreactant, carrier or diluent gas such as hydrogen is passed through a hole within a high emissivity, thin, insulating septum into the reaction chamber above the melting point of silicon. The thin septum has one face below the decomposition temperature of the gas and an opposite face exposed to the reaction chamber. Thus, the precursor gas is decomposed directly to silicon in the reaction chamber. Any stream of decomposition gas and any unreacted precursor gas from the reaction chamber is removed. A carbon or graphite preform object placed in the reaction chamber is contacted with the silicon. The carbon or graphite preform object is recovered from the reactor chamber after it has been converted to a desired silicon carbide, silicon and carbon composition.
A computer program called dsn config converter automates what had been a manual process for updating the multimission adaptation file (multi.aaf) used by a multiple-mission-command-sequence-generating process comprised of a combination of the AUTOGEN and APGEN programs mentioned in the immediately preceding article. The program converts the dsn_config.cvf file that provides DSN (Deep Space Network) antenna configuration code mappings from a context variable file (CVF) format used in another part of the command generation process to an APGEN activity file (AAF) format used by AUTOGEN and APGEN. Whereas previously, the information in the dsn_config.cvf file was manually encoded into the multi.aaf file, now the program automatically generates a dsn_config.aaf file from the dsn_config.cvf file. As part of this development effort the multi.aaf file was adapted to use the new dsn_config.aaf representations. Through this automation a tedious error-prone step has now been replaced by a quick and robust step.
A computer program converts, into a format suitable for processing on Earth, files of downlinked telemetric data pertaining to the operation of the Instrument Deployment Device (IDD), which is a robot arm on either of the Mars Explorer Rovers (MERs). The raw downlinked data files are in comma-separated- value (CSV) format. The present program converts the files into Rover Kinematics State Markup Language (RKSML), which is an Extensible Markup Language (XML) format that facilitates representation of operations of the IDD and enables analysis of the operations by means of the Rover Sequencing Validation Program (RSVP), which is used to build sequences of commanded operations for the MERs. After conversion by means of the present program, the downlinked data can be processed by RSVP, enabling the MER downlink operations team to play back the actual IDD activity represented by the telemetric data against the planned IDD activity. Thus, the present program enhances the diagnosis of anomalies that manifest themselves as differences between actual and planned IDD activities.