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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 613 records · Page 34
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Global Electric Circuit Implications of Combined Aircraft Storm Electric Current Measurements and Satellite-Based Diurnal Lightning Statistics

Using rotating vane electric field mills and Gerdien capacitors, we measured the electric field profile and conductivity during 850 overflights of thunderstorms and electrified shower clouds (ESCs) spanning regions including the Southeastern United States, the Western Atlantic Ocean, the Gulf of Mexico, Central America and adjacent oceans, Central Brazil, and the South Pacific. The overflights include storms over land and ocean, and with positive and negative fields above the storms. Over three-quarters (78%) of the land storms had detectable lightning, while less than half (43%) of the oceanic storms had lightning. Integrating our electric field and conductivity data, we determined total conduction currents and flash rates for each overpass. With knowledge of the storm location (land or ocean) and type (with or without lightning), we determine the mean currents by location and type. The mean current for ocean thunderstorms is 1.7 A while the mean current for land thunderstorms is 1.0 A. The mean current for ocean ESCs 0.41 A and the mean current for land ESCs is 0.13 A. We did not find any significant regional or latitudinal based patterns in our total conduction currents. By combining the aircraft derived storm currents and flash rates with diurnal flash rate statistics derived from the Lightning Imaging Sensor (LIS) and Optical Transient Detector (OTD) low Earth orbiting satellites, we reproduce the diurnal variation in the global electric circuit (i.e., the Carnegie curve) to within 4% for all but two short periods of time. The agreement with the Carnegie curve was obtained without any tuning or adjustment of the satellite or aircraft data. Given our data and assumptions, mean contributions to the global electric circuit are 1.1 kA (land) and 0.7 kA (ocean) from thunderstorms, and 0.22 kA (ocean) and 0.04 (land) from ESCs, resulting in a mean total conduction current estimate for the global electric circuit of 2.0 kA. Mean storm counts are 1100 for land thunderstorms, 530 for ocean ESCs, 390 for ocean thunderstorms, and 330 for land ESCs.

Mach, Douglas M.↗
NASA NTRS2011

Conformal Thin Film Packaging for SiC Sensor Circuits in Harsh Environments

In this investigation sputtered silicon carbide annealed at 300 C for one hour is used as a conformal thin film package. A RF magnetron sputterer was used to deposit 500 nm silicon carbide films on gold metal structures on alumina wafers. To determine the reliability and resistance to immersion in harsh environments, samples were submerged in gold etchant for 24 hours, in BOE for 24 hours, and in an O2 plasma etch for one hour. The adhesion strength of the thin film was measured by a pull test before and after the chemical immersion, which indicated that the film has an adhesion strength better than 10(exp 8) N/m2; this is similar to the adhesion of the gold layer to the alumina wafer. MIM capacitors are used to determine the dielectric constant, which is dependent on the SiC anneal temperature. Finally, to demonstrate that the SiC, conformal, thin film may be used to package RF circuits and sensors, an LC resonator circuit was fabricated and tested with and without the conformal SiC thin film packaging. The results indicate that the SiC coating adds no appreciable degradation to the circuits RF performance. Index Terms Sputter, silicon carbide, MIM capacitors, LC resonators, gold etchants, BOE, O2 plasma

Scardelletti, Maximilian C.↗
NASA NTRS2009

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Neudeck, Philip G.↗
NASA NTRS2011

Digi Island: A Serious Game for Teaching and Learning Digital Circuit Optimization

Karnaugh maps, also known as K-maps, are a tool used to optimize or simplify digital logic circuits. A K-map is a graphical display of a logic circuit. K-map optimization is essentially the process of finding a minimum number of maximal aggregations of K-map cells. with values of 1 according to a set of rules. The Digi Island is a serious game designed for aiding students to learn K-map optimization. The game takes place on an exotic island (called Digi Island) in the Pacific Ocean . The player is an adventurer to the Digi Island and will transform it into a tourist attraction by developing real estates, such as amusement parks.and hotels. The Digi Island game elegantly converts boring 1s and Os in digital circuits into usable and unusable spaces on a beautiful island and transforms K-map optimization into real estate development, an activity with which many students are familiar and also interested in. This paper discusses the design, development, and some preliminary results of the Digi Island game.

Harper, Michael↗
NASA NTRS2011

AC Read-Out Circuits for Single Pixel Characterization of TES Microcalorimeters and Bolometers

SRON is developing Frequency Domain Multiplexing (FDM) for the read-out of transition edge sensor (TES) soft x-ray microcalorimeters for the XMS instrument of the International X-ray Observatory and far-infrared bolometers for the SAFARI instrument on the Japanese mission SPICA. In FDM the TESs are AC voltage biased at frequencies from 0.5 to 6 MHz in a superconducting LC resonant circuit and the signal is read-out by low noise and high dynamic range SQUIDs amplifiers. The TES works as an amplitude modulator. We report on several AC bias experiments performed on different detectors. In particular, we discuss the results on the characterization of Goddard Space Flight Center x-ray pixels and SRON bolometers. The paper focuses on the analysis of different read-out configurations developed to optimize the noise and the impedance matching between the detectors and the SQUID amplifier. A novel feedback network electronics has been developed to keep the SQUID in flux locked loop, when coupled to superconducting high Q circuits, and to optimally tune the resonant bias circuit. The achieved detector performances are discussed in view of the instrument requirement for the two space missions.

Gottardi, L.↗
NASA NTRS2009

Improving Heat Transfer Performance of Printed Circuit Boards

This paper will explore the ability of printed circuit boards laminated with a Carbon Core Laminate to transfer heat vs. standard printed circuit boards that use only thick layers of copper. The paper will compare the differences in heat transfer performance of printed circuit boards with and without CCL.

Schatzel, Donald V.↗
NASA NTRS2008

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

Neudeck, Philip G.↗
NASA NTRS2016

Numerical Simulation of a Complete Low-Speed Wind Tunnel Circuit

A numerical simulation of the complete circuit of the NASA Langley 14 x 22-ft low-speed wind tunnel is described. Inside the circuit, all turning vanes are modeled as well as the five flow control vanes downstream of the 1st corner. The fan drive system is modeled using an actuator disk for the fan blades coupled with the fan nacelle. All the surfaces are modeled as viscous walls except the turning vanes, which were modeled as inviscid surfaces. NASA Langley's TetrUSS unstructured grid software was used for grid generation and flow simulation. Two turbulence models were employed in the present study, namely, the one-equation Spalart-Allmaras model and the shear stress transport (SST) model of Menter. The paper shows the flow characteristics in the circuit and compares the results with experimental data where available.

Nayani, Sudheer N.↗
NASA NTRS2017

Hybrid Direct-Current Circuit Breaker

A circuit breaking system includes a first branch including at least one solid-state snubber; a second branch coupled in parallel to the first branch and including a superconductor and a cryogenic contactor coupled in series; and a controller operatively coupled to the at least one solid-state snubber and the cryogenic contactor and programmed to, when a fault occurs in the load circuit, activate the at least one solid-state snubber for migrating flow of the electrical current from the second branch to the first branch, and, when the fault is cleared in the load circuit, activate the cryogenic contactor for migrating the flow of the electrical current from the first branch to the second branch.

Wang, Ruxi↗
NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Silicon Carbid↗
NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Spry, David J.↗
NASA NTRS2018

Interconnection of Semiconductor Devices in Extreme Environment Microelectronic Integrated Circuit Chips

A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).

Spry, David J.↗
NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗
NASA NTRSDate not supplied

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire -bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500°C are reviewed.

High Temperature, Packaging, Alumina, Thick Film↗
NASA NTRSDate not supplied

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3 ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3 ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire - bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500oC are reviewed.

high temperature↗
DOE OSTI2021

Integrated circuit authentication from a die material measurement

The various technologies presented herein relate to measuring a signal generated by a die-based test circuit incorporated into an IC and utilizing the measured signal to authenticate the IC. The signal can be based upon a sensor response generated by the test circuit fabricated into the die, wherein the sensor response is based upon a property of the die material. The signal can be compared with a reference value obtained from one or more test circuit(s) respectively located on one or more reference dies, wherein the reference dies are respectively cut from different wafers, and the location at which the reference dies were cut is known. If the measured signal matches the reference value, the die is deemed to be from the same cut location as the dies from which the reference value was obtained. If the measured signal does not match the reference value, the die is not authenticated.

Zortman, William A.↗
DOE OSTI2021

Large scale multi-node simulations of $\mathbb{Z}_2$ gauge theory quantum circuits using Google Cloud Platform

Simulating quantum field theories on a quantum computer is one of the most exciting fundamental physics applications of quantum information science. Dynamical time evolution of quantum fields is a challenge that is beyond the capabilities of classical computing, but it can teach us important lessons about the fundamental fabric of space and time. Whether we may answer scientific questions of interest using near-term quantum computing hardware is an open question that requires a detailed simulation study of quantum noise. Here we present a large scale simulation study powered by a multi-node implementation of qsim using the Google Cloud Platform. We additionally employ newly-developed GPU capabilities in qsim and show how Tensor Processing Units -- Application-specific Integrated Circuits (ASICs) specialized for Machine Learning -- may be used to dramatically speed up the simulation of large quantum circuits. We demonstrate the use of high performance cloud computing for simulating $\mathbb{Z}_2$ quantum field theories on system sizes up to 36 qubits. We find this lattice size is not able to simulate our problem and observable combination with sufficient accuracy, implying more challenging observables of interest for this theory are likely beyond the reach of classical computation using exact circuit simulation.

Gustafson, Erik↗
DOE OSTI2021

Simulations of Quantum Circuits with Approximate Noise using qsim and Cirq

We introduce multinode quantum trajectory simulations with qsim, an open source high performance simulator of quantum circuits. qsim can be used as a backend of Cirq, a Python software library for writing quantum circuits. We present a novel delayed inner product algorithm for quantum trajectories which can result in an order of magnitude speedup for low noise simulation. We also provide tools to use this framework in Google Cloud Platform, with high performance virtual machines in a single mode or multinode setting. Multinode configurations are well suited to simulate noisy quantum circuits with quantum trajectories. Finally, we introduce an approximate noise model for Google's experimental quantum computing platform and compare the results of noisy simulations with experiments for several quantum algorithms on Google's Quantum Computing Service.

Isakov, Sergei V.↗