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Programmatic Impact of SDRAM SEFI
The Elpida EDS5104(08)ABTA 512Mb SDRAM is examined for programmatic impact of SEE. Use cases for the devices including EDAC and mode register reload are examined. Results indicate some SEE mitigation methods require careful application to achieve system-level benefits, while some event types are essentially mitigated by the application use. In the studied devices MBE and SEFI are identified and investigated as mechanisms requiring special consideration.
Programmable Logic Device (PLD) Design Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio
The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. At the conclusion of the development, the software and hardware description language (HDL) code was delivered to JSC for their use in their iPAS test bed to get hands-on experience with the STRS standard, and for development of their own STRS Waveforms on the now STRS compliant platform.The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe the design of the HDL code for the FPGA portion of the iPAS STRS Radio particularly the design of the FPGA wrapper and the test waveform.
Hardware Interface Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio Ssystem (STRS) Radio
The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.
Waveform Developer's Guide for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio
The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx(Trademark) ML605 Virtex(Trademark)-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek(Trademark) eBox 620-110-FL) running the Ubuntu 12.4 operating system. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications. The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.
Vorago RH-OBC-1 Single Event Effect Characterization Test Report
The Vorago Technologies RH-OBC-1 is a CubeSat Kit Bus compatible single board computer with a Vorago VA10820 ARM Cortex-M0 microcontroller at its core. The board also includes a set of common peripheral integrated circuits, like voltage regulators, non-volatile memories (NVM), an analog-to-digital converter (ADC), a watchdog/supervisor, and a Controller Area Network (CAN) bus transceiver. High-energy proton (200 MeV) testing was conducted at both board and component levels to investigate single-event effects.
Increasing Radon Daughter Plate-out onto Superconducting Qubits
Radon daughter plate-out may pose a fundamental limitation to realizing large-scale superconducting quantum computers. Radon daughters plated-out on a superconducting qubit can decay, releasing energy into the substrate, producing phonons. Phonon-induced quasiparticles then generate bit-flip errors and reduce coherence times. We seek to increase plate-out on chips to enable future study of the impact of radon on coherence times. In this project, we utilize COMSOL Multiphysics simulations to visualize electric field configuration and model ion transport to finalize design of a device to increase radon plate-out on qubit chips.
High density bit transition requirements versus the effects on BCH error correcting code
The design to achieve the required bit transition density for the Space Shuttle high rate multiplexes (HRM) data stream of the Space Laboratory Vehicle is reviewed. It contained a recommended circuit approach, specified the pseudo random (PN) sequence to be used and detailed the properties of the sequence. Calculations showing the probability of failing to meet the required transition density were included. A computer simulation of the data stream and PN cover sequence was provided. All worst case situations were simulated and the bit transition density exceeded that required. The Preliminary Design Review and the critical Design Review are documented. The Cover Sequence Generator (CSG) Encoder/Decoder design was constructed and demonstrated. The demonstrations were successful. All HRM and HRDM units incorporate the CSG encoder or CSG decoder as appropriate.
A study of digital holographic filters generation. Phase 2: Digital data communication system, volume 1
An empirical study of the performance of the Viterbi decoders in bursty channels was carried out and an improved algebraic decoder for nonsystematic codes was developed. The hybrid algorithm was simulated for the (2,1), k = 7 code on a computer using 20 channels having various error statistics, ranging from pure random error to pure bursty channels. The hybrid system outperformed both the algebraic and the Viterbi decoders in every case, except the 1% random error channel where the Viterbi decoder had one bit less decoding error.
Spacelab high density digital recorders
The design and performance of the high-density digital recorder (HDDR) developed for use at the NASA centers (KSC, JSC, and GSFC) and at the JPL to store and retrieve 50-Mb/s PCM data streams from the Spacelab experiments are reported. The recording reproduction, and transport requirements are reviewed; and the design solutions adopted in the final version of the HDDR are described, incuding three-position-modulation and Y-phase encoding, microprocessor-controlled automatic bit synchronization and equalization, cyclic-redundancy-check error detection and correction, clock regeneration, data and clock variations, tape-speed control, and EEE-488 remote control. Reliable performance, with bit error rates 1 in 10 to the 10th forward and 1 in 10 to the 9th reverse or better and packing density up to 50 percent greater than that obtainable using conventional codes, is reported after 1.5 years of service.
Reliable voltage scaled links for compressed data
Systems, apparatuses, and methods for reliably transmitting data over voltage scaled links are disclosed. A computing system includes at least first and second devices connected via a link. In one implementation, if a data block can be compressed to less than or equal to half the original size of the data block, then the data block is compressed and sent on the link in a single clock cycle rather than two clock cycles. If the data block cannot be compressed to half the original size, but if the data block can be compressed enough to include error correction code (ECC) bits without exceeding the original size, then ECC bits are added to the compressed block which is sent on the link at a reduced voltage. The ECC bits help to correct for any errors that are generated as a result of operating the link at the reduced voltage.
Spin glasses and error-correcting codes
In this article, we study a model for error-correcting codes that comes from spin glass theory and leads to both new codes and a new decoding technique. Using the theory of spin glasses, it has been proven that a simple construction yields a family of binary codes whose performance asymptotically approaches the Shannon bound for the Gaussian channel. The limit is approached as the number of information bits per codeword approaches infinity while the rate of the code approaches zero. Thus, the codes rapidly become impractical. We present simulation results that show the performance of a few manageable examples of these codes. In the correspondence that exists between spin glasses and error-correcting codes, the concept of a thermal average leads to a method of decoding that differs from the standard method of finding the most likely information sequence for a given received codeword. Whereas the standard method corresponds to calculating the thermal average at temperature zero, calculating the thermal average at a certain optimum temperature results instead in the sequence of most likely information bits. Since linear block codes and convolutional codes can be viewed as examples of spin glasses, this new decoding method can be used to decode these codes in a way that minimizes the bit error rate instead of the codeword error rate. We present simulation results that show a small improvement in bit error rate by using the thermal average technique.
Simulations for Full Unit-memory and Partial Unit-memory Convolutional Codes with Real-time Minimal-byte-error Probability Decoding Algorithm
A program which was written to simulate Real Time Minimal-Byte-Error Probability (RTMBEP) decoding of full unit-memory (FUM) convolutional codes on a 3-bit quantized AWGN channel is described. This program was used to compute the symbol-error probability of FUM codes and to determine the signal to noise (SNR) required to achieve a bit error rate (BER) of 10 to the minus 6th power for corresponding concatenated systems. A (6,6/30) FUM code, 6-bit Reed-Solomon code combination was found to achieve the required BER at a SNR of 1.886 dB. The RTMBEP algorithm was then modified for decoding partial unit-memory (PUM) convolutional codes. A simulation program was also written to simulate the symbol-error probability of these codes.
Bandwidth compression of synthetic aperture radar imagery by quantization of raw radar data
A study is made of the effects of quantization of the radar returns transmitted from aircraft or spacecraft employing a synthetic aperture radar system. The study is based on the output images obtained after one-bit, two-bit, and eight-bit quantizations and comparing the results to ground truth. In this way the degradation resulting from data or bandwidth reduction is determined. Quantization is evaluated in terms of crater scene, number of looks, and transmission error rate. It is found that two-bit quantization of raw radar data from homogeneous scenes processed to 32 looks yields nearly all the details of the original. One-bit quantization of raw radar data from homogeneous scenes processed to 32 looks yields a good visual representation of the scene but some fine detail is lost and the absolute reflectivity level is not reliable. Image quality is observed to improve with more looks and video and intermediate frequency quantization are not distinguishable even for one-bit quantizations. Image quality is not influenced by bit error rates less than about 2 to the -7th power.
A study of high density bit transition requirements versus the effects on BCH error correcting codes
The use of PN sequence generators to create a minimum number of transitions in an NRZ bit stream is described. The CSG encoder/decoder design was constructed and demonstrated.
Odd-bit symmetric QASK
Multiple-amplitude and phase-shift-keyed (MAPSK) signal set selection is influenced by factors such as average and/or peak signal-to-noise ratio for a given error probability, dynamic range of signal amplitudes, simplicity of generation and detection, and number of bit errors per adjacent symbol error. This paper compares two possible quadrature-amplitude-shift-keyed (QASK) signal sets for the case where the number of bits per symbol is odd (for the even-bit case, the square array is the only viable QASK choice). The symmetric QASK version out-performs the rectangular QASK set at a very modest implementation penalty. This permits symmetric QASK to be considered in future odd-bit system studies.