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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 613 records · Page 34

All sources NASA NTRS DOE OSTI

NASA NTRS1992

Joint Japan/U.S. Conference on Adaptive Structures, 2nd, Nagoya, Japan, Nov. 12-14, 1991, Collection of Papers

The present conference discusses the development status of adaptive structures in Europe and in Japan, the 'Cosmo-Lab' structures/robotics cooperation concept, active-adhesion concepts for in-orbit structural assembly, adaptively controlled truss structures, object-oriented modeling in structural analysis, the control effectiveness and energy efficiency of an active mass damper, a space truss with experimental tendon control, and piezoelectric actuator-based space trusses. Also discussed is the control of resonant frequencies in adaptive structures through prestressing, active control of vortex-excited vibrations of flexible cylindrical structures, shape adjustment of a flexible space antenna reflector, the SDIO Adaptive Structures Program, optimal trajectories of iterative manipulation for space robots, a docking device as an adaptive structure, shape-memory polymers and their hybrid composites, and fuzzy control methods for structural dynamics.

Matsuzaki, Yuji↗

NASA NTRS1993

High-speed joint-transform optical image correlator using GaAs/AlGaAs semi-insulating multiple quantum wells and diode lasers

We demonstrate a compact real-time optical image correlator using diode lasers and a semi-insulating GaAs/AlGaAs multiple-quantum-well (SI-MQW) device as the holographic element. With only 3 mW of power incident upon the SI-MQW device, the correlation is obtained in 1 microsec and can be erased in as fast as 2 microsec, which presents the possibility of a system capable of 3 x 10 exp 5 correlations/s. We also show that images can be stored for a controllable length of time (2-25 microsec), which presents possibilities for the use of the SI-MQW device as a data or image buffer memory.

Partovi, A.↗

NASA NTRS1996

The Single Event Effect Characteristics of the 486-DX4 Microprocessor

This research describes the development of an experimental radiation testing environment to investigate the single event effect (SEE) susceptibility of the 486-DX4 microprocessor. SEE effects are caused by radiation particles that disrupt the logic state of an operating semiconductor, and include single event upsets (SEU) and single event latchup (SEL). The relevance of this work can be applied directly to digital devices that are used in spaceflight computer systems. The 486-DX4 is a powerful commercial microprocessor that is currently under consideration for use in several spaceflight systems. As part of its selection process, it must be rigorously tested to determine its overall reliability in the space environment, including its radiation susceptibility. The goal of this research is to experimentally test and characterize the single event effects of the 486-DX4 microprocessor using a cyclotron facility as the fault-injection source. The test philosophy is to focus on the "operational susceptibility," by executing real software and monitoring for errors while the device is under irradiation. This research encompasses both experimental and analytical techniques, and yields a characterization of the 486-DX4's behavior for different operating modes. Additionally, the test methodology can accommodate a wide range of digital devices, such as microprocessors, microcontrollers, ASICS, and memory modules, for future testing. The goals were achieved by testing with three heavy-ion species to provide different linear energy transfer rates, and a total of six microprocessor parts were tested from two different vendors. A consistent set of error modes were identified that indicate the manner in which the errors were detected in the processor. The upset cross-section curves were calculated for each error mode, and the SEU threshold and saturation levels were identified for each processor. Results show a distinct difference in the upset rate for different configurations of the on-chip cache, as well as proving that one vendor is superior to the other in terms of latchup susceptibility. Results from this testing were also used to provide a mean-time-between-failure estimate of the 486-DX4 operating in the radiation environment for the International Space Station.

Kouba, Coy↗

NASA NTRS2009

Compact, Low-Overhead, MIL-STD-1553B Controller

A compact and flexible controller has been developed to provide MIL-STD- 1553B Remote Terminal (RT) communications and supporting and related functions with minimal demand on the resources of the system in which the controller is to be installed. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD-1553B is commonly used in defense and space applications.) Many other MIL-STD-1553B RT controllers are complicated, and to enable them to function, it is necessary to provide software and to use such ancillary separate hardware devices as microprocessors and dual-port memories. The present controller functions without need for software and any ancillary hardware. In addition, it contains a flexible system interface and extensive support hardware while including on-chip error-checking and diagnostic support circuitry. This controller is implemented within part of a modern field-programmable gate array.

Katz, Richard↗

NASA NTRS2011

High-Temperature Smart Structures for Engine Noise Reduction and Performance Enhancement

One of key NASA goals is to develop and integrate noise reduction technology to enable unrestricted air transportation service to all communities. One of the technical priorities of this activity has been to account for and reduce noise via propulsion/airframe interactions, identifying advanced concepts to be integrated with the airframe to mitigate these noise-producing mechanisms. An adaptive geometry chevron using embedded smart structures technology offers the possibility of maximizing engine performance while retaining and possibly enhancing the favorable noise characteristics of current designs. New high-temperature shape memory alloy (HTSMA) materials technology enables the devices to operate in both low-temperature (fan) and high-temperature (core) exhaust flows. Chevron-equipped engines have demonstrated reduced noise in testing and operational use. It is desirable to have the noise benefits of chevrons in takeoff/landing conditions, but have them deployed into a minimum drag position for cruise flight. The central feature of the innovation was building on rapidly maturing HTSMA technology to implement a next-generation aircraft noise mitigation system centered on adaptive chevron flow control surfaces. In general, SMA-actuated devices have the potential to enhance the demonstrated noise reduction effectiveness of chevron systems while eliminating the associated performance penalty. The use of structurally integrated smart devices will minimize the mechanical and subsystem complexity of this implementation. The central innovations of the effort entail the modification of prior chevron designs to include a small cut that relaxes structural stiffness without compromising the desired flow characteristics over the surface; the reorientation of SMA actuation devices to apply forces to deflect the chevron tip, exploiting this relaxed stiffness; and the use of high-temperature SMA (HTSMA) materials to enable operation in the demanding core chevron environment. The overall conclusion of these design studies was that the cut chevron concept is a critical enabling step in bringing the variable geometry core chevron within reach. The presence of the cut may be aerodynamically undesirable in some respects, but it is present only when the chevron is not immersed in the core jet exhaust. When deployed, the gap closes as the chevron tip enters the high-speed, high-temperature core stream. Aeroacoustic testing and flow visualization support the contention that this cut is inconsequential to chevron performance.

Quackenbush, Todd R.↗

DOE OSTI2021

Method and apparatus for using compression to improve performance of low voltage caches

A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

Kalamatianos, John↗

DOE OSTI2021

Electronic device and method for compressing sampled data

An electronic device for compressing sampled data comprises a memory element and a processing element. The memory element is configured to store sampled data points and sampled times. The processing element is in electronic communication with the memory element and is configured to receive a plurality of sampled data points, a slope for each sampled data point in succession, the slope being a value of a change between the sampled data point and its successive sampled data point, and store the sampled data point in the memory element when the slope changes in value from a previous sampled data point.

Morrow, Mitchell Hedges↗

DOE OSTI2021

Electronic device and method for compressing sampled data

Tohlen, Michael Aaron↗

DOE OSTI2021

Electronic device and method for compressing sampled data

Morrow, Mitchell Hedges↗

NASA NTRS1973

Planar electroluminescent panel techniques

Investigations of planar electroluminescent multipurpose displays with latch-in memory are described. An 18 x 24 in. flat, thin address panel with elements spacing of 0.100 in. was constructed which demonstrated essentially uniform luminosity of 3-5 foot lamberts for each of its 43200 EL cells. A working model of a 4-bit EL-PC (electroluminescent photoconductive) electrooptical decoder was made which demonstrated the feasibility of this concept. A single-diagram electroluminescent display device with photoconductive-electroluminescent latch-in memory was constructed which demonstrated the conceptual soundness of this principle. Attempts to combine these principles in a single PEL multipurpose display with latch-in memory were unsuccessful and were judged to exceed the state-of-the-art for close-packed (0.10 in. centers) photoconductor-electroluminescent cell assembly.

Kerr, C.↗

NASA NTRS2009

Radiation tests of highly scaled high density commercial nonvolatile NAND flash memories update 2009

Heavy ion single-event measurements on a variety of high density commercial NAND flash memories are reported. Three single event effect (SEE) phenomena are examined: single effect upsets (SEUs), single event functional interrupts (SEFIs), and catastrophic loss of ability to erase and program the device. Also, radiation results of multilevel flash technology are compared with results from single-level flash technology. These commercial high density memories appear to be much less susceptible to SEE and have better TID response compared to older generations of flash memories. The single-level devices are less sensitive to SEUs than multi-level devices. The charge pump in this study survived up to 600 krads. A new high current phenomenon in high density NAND flash memories is also discussed.

Nguyen, Duc N.↗

DOE OSTI2021

JTAG-based PLC memory acquisition framework for industrial control systems

In industrial control systems (ICS), programmable logic controllers (PLC) are the embedded devices that directly control and monitor critical industrial infrastructure processes such as nuclear plants and power grid stations. Cyberattacks often target PLCs to sabotage a physical process. A memory forensic analysis of a suspect PLC can answer questions about an attack, including compromised firmware and manipulation of PLC control logic code and I/O devices. Given physical access to a PLC, collecting forensic information from the PLC memory at the hardware-level is risky and challenging. It may cause the PLC to crash or hang since PLCs have proprietary, legacy hardware with heterogeneous architecture. This paper addresses this research problem and proposes a novel JTAG (Joint Test Action Group)-based framework, Kyros, for reliable PLC memory acquisition. Kyros systematically creates a JTAG profile of a PLC through hardware assessment, JTAG pins identification, memory map creation, and optimizing acquisition parameters. It also facilitates the community of interest (such as ICS owners, operators, and vendors) to develop the JTAG profiles of PLCs. Further, we present a case study of Kyros implementation over Allen-Bradley 1756-A10/B to help understand the framework's application on a real-world PLC used in industry settings. The sample PLC memory dumps are shared with the research community to facilitate further research.

Rais, Muhammad Haris↗

NASA NTRS1985

Synchronous clock stopper for microprocessor

A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.

Kitchin, David A.↗

NASA NTRS1976

A high speed imaging system for nuclear diagnostics

A high speed imaging system based on state-of-the-art photosensor arrays was designed for use in nuclear diagnostics. The system is comprised of a front end rapid scan solid state camera, a high speed digitizer, and a PCM line driver in a downhole package and a memory buffer system in an uphole trailer. The downhole camera takes a snapshot of a nuclear device created flux stream, digitizes the image and transmits it to the uphole memory system before being destroyed. The memory system performs two functions: it retains the data for local display and processing by a microprocessor, and it buffers the data for retransmission at slower rates to a computational facility. In the talk, the impetus for such a system as well as its operation was discussed, along with systems under development which incorporate higher data rates and more resolution.

Eyer, H. H.↗

NASA NTRS1987

Advanced development of double-injection, deep-impurity semiconductor switches

Deep-impurity, double-injection devices, commonly refered to as (DI) squared devices, represent a class of semiconductor switches possessing a very high degree of tolerance to electron and neutron irradiation and to elevated temperature operation. These properties have caused them to be considered as attractive candidates for space power applications. The design, fabrication, and testing of several varieties of (DI) squared devices intended for power switching are described. All of these designs were based upon gold-doped silicon material. Test results, along with results of computer simulations of device operation, other calculations based upon the assumed mode of operation of (DI) squared devices, and empirical information regarding power semiconductor device operation and limitations, have led to the conculsion that these devices are not well suited to high-power applications. When operated in power circuitry configurations, they exhibit high-power losses in both the off-state and on-state modes. These losses are caused by phenomena inherent to the physics and material of the devices and cannot be much reduced by device design optimizations. The (DI) squared technology may, however, find application in low-power functions such as sensing, logic, and memory, when tolerance to radiation and temperature are desirable (especially is device performance is improved by incorporation of deep-level impurities other than gold.

Hanes, M. H.↗

DOE OSTI2024

GPU-enabled extreme-scale turbulence simulations: Fourier pseudo-spectral algorithms at the exascale using OpenMP offloading

Fourier pseudo-spectral methods for nonlinear partial differential equations are of wide interest in many areas of advanced computational science, including direct numerical simulation of three-dimensional (3-D) turbulence governed by the Navier-Stokes equations in fluid dynamics. This paper presents a new capability for simulating turbulence at a new record resolution up to 35 trillion grid points, on the world's first exascale computer, Frontier, comprising AMD MI250x GPUs with HPE's Slingshot interconnect and operated by the US Department of Energy's Oak Ridge Leadership Computing Facility (OLCF). Key programming strategies designed to take maximum advantage of the machine architecture involve performing almost all computations on the GPU which has the same memory capacity as the CPU, performing all-to-all communication among sets of parallel processes directly on the GPU, and targeting GPUs efficiently using OpenMP offloading for intensive number-crunching including 1-D Fast Fourier Transforms (FFT) performed using AMD ROCm library calls. With 99% of computing power on Frontier being on the GPU, leaving the CPU idle leads to a net performance gain via avoiding the overhead of data movement between host and device except when needed for some I/O purposes. Memory footprint including the size of communication buffers for MPI_ALLTOALL is managed carefully to maximize the largest problem size possible for a given node count. Detailed performance data including separate contributions from different categories of operations to the elapsed wall time per step are reported for five grid resolutions, from 2048 3 on a single node to 32768 3 on 4096 or 8192 nodes out of 9408 on the system. Both 1D and 2D domain decompositions which divide a 3D periodic domain into slabs and pencils respectively are implemented. The present code suite (labeled by the acronym GESTS, GPUs for Extreme Scale Turbulence Simulations) achieves a figure of merit (in grid points per second) exceeding goals set in the Center for Accelerated Application Readiness (CAAR) program for Frontier. The performance attained is highly favorable in both weak scaling and strong scaling, with notable departures only for 2048 3 where communication is entirely intra-node, and for 32768 3 , where a challenge due to small message sizes does arise. Communication performance is addressed further using a lightweight test code that performs all-to-all communication in a manner matching the full turbulence simulation code. Performance at large problem sizes is affected by both small message size due to high node counts as well as dragonfly network topology features on the machine, but is consistent with official expectations of sustained performance on Frontier. Overall, although not perfect, the scalability achieved at the extreme problem size of 32768 3 (and up to 8192 nodes — which corresponds to hardware rated at just under 1 exaflop/sec of theoretical peak computational performance) is arguably better than the scalability observed using prior state-of-the-art algorithms on Frontier's predecessor machine (Summit) at OLCF. New science results for the study of intermittency in turbulence enabled by this code and its extensions are to be reported separately in the near future.

3D fast Fourier transform↗

NASA NTRS1991

Data systems and computer science space data systems: Onboard memory and storage

The topics are presented in viewgraph form and include the following: technical objectives; technology challenges; state-of-the-art assessment; mass storage comparison; SODR drive and system concepts; program description; vertical Bloch line (VBL) device concept; relationship to external programs; and backup charts for memory and storage.

Shull, Tom↗

NASA NTRS2008

Characterization of Ni19.5Ti50.5Pd25Pt5 High-Temperature Shape Memory Alloy Springs and their Potential Application in Aeronautics

Shape memory alloys (SMAs) have been used as actuators in many different industries since the discovery of the shape memory effect, but the use of SMAs as actuation devices in aeronautics has been limited due to the temperature constraints of commercially available materials. Consequently, work is being done at NASA's Glenn Research Center to develop new SMAs capable of being used in high temperature environments. One of the more promising high-temperature shape memory alloys (HTSMAs) is Ni19.5Ti50.5Pd25Pt5. Recent work has shown that this material is capable of being used in operating environments of up to 250 C. This material has been shown to have very useful actuation capabilities, demonstrating repeatable strain recoveries up to 2.5% in the presence of an externally applied load. Based on these findings, further work has been initiated to explore potential applications and alternative forms of this alloy, such as springs. Thus, characterization of Ni19.5Ti50.5Pd25Pt5 springs, including their mechanical response and how variations in this response correlate to changes in geometric parameters, are discussed. The effects of loading history, or training, on spring behavior were also investigated. A comparison of the springs with wire actuators is made and the benefits of using one actuator form as opposed to the other discussed. These findings are used to discuss design considerations for a surge-control mechanism that could be used in the centrifugal compressor of a T-700 helicopter engine.

Stebner, Aaron↗