Effect of silicon oxide thickness on polysilicon based passivated contacts for high-efficiency crystalline silicon solar cells
In this paper, we have investigated the effect of SiO x thickness (1-3 nm) on the performance of polycrystalline (poly) Si/SiO x /monocrystalline Si ( c -Si) passivated contacts. Our results show that for both n- and p-type contacts, there is an optimum SiO x thickness of 1.4-1.6 nm for obtaining the highest implied open-circuit voltage ( i-V oc ) values of ~739 and ~700 mV, respectively. For contacts with SiO x thicker than 1.6 nm, the i-V oc drops due to reduced field-effect passivation. We attribute this to the fact that a thicker SiO x layer hinders the diffusion of both n- and p-type dopants into the c-Si wafer resulting in a junction that is very close to the c -Si/SiO x interface, which increases carrier recombination most likely due to the presence of defects at this interface. The resistivity measured through the metal/poly-Si/SiO x / c -Si stack is independent of SiO x thickness up to 1.6 nm, and increases exponentially by several orders of magnitude with further increase in SiO x thickness due to inefficient tunneling transport. Finally, the extent of metallization-induced degradation of the poly-Si/SiO x / c -Si contacts is worst for the thinnest SiO x investigated (~1 nm), and interestingly it is not completely mitigated even for a ~3 nm thick SiO x .