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At least 595 records · Page 33

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

Fabrication of a prototype large capacity multiple blade slurry saw is considered. Design of the bladehead which will tension up to 1000 blades, and cut a 45 cm long silicon ingot as large as 12 cm in diameter is given. The large blade tensioning force of 270,000 kg is applied through two bolts acting on a pair of scissor toggles, significantly reducing operator set-up time. Tests with an upside-down cutting technique resulted in 100% wafering yields and the highest wafer accuracy yet experienced with MS slicing. Variations in oil and abrasives resulted only in degraded slicing results. A technique of continuous abrasive slurry separation to remove silicon debris is described.

Holden, S. C.↗

Some observations on the characteristics of low-cost silicon sheets

To meet the need for low cost silicon sheet material in the ERDA/JPL photovoltaics program, JPL has initiated a wide ranging technology development effort in crystal growth that includes several different technology thrusts. They range in scope from innovative ingot growth and multislice wafering, to shaped growth techniques, substrate-related processes and hot forming techniques. In this paper, some salient observations on materials resulting from these processes are reported. Included are multiblade wafering-induced damage studies, interface morphology studies on the heat exchanger cast silicon, some diffusion length measurements in thin silicon layers on ceramic substrates, and results on the equilibrium structure found in laser zone ribbon growth.

Digges, T. G., Jr.↗

The effect of oxidation-expanded defects upon MOS parameters

Implantation of Ne ions was chosen as a means of introducing a uniformly distributed quantitatively controllable and reproducible amount of microdefects at the silicon surface. Each wafer was ion-implanted on one half of its surface, the other half remaining as a control. Seven implant fluences from 1 trillion to 5 by 10 to the 14th power Ne ions/sq cm were used. The fluences, as well as the concentrations of defects expanded by the subsequent gate oxidation, were correlated with seven different MOS parameters. For implant fluences of 10 to the 14th power per sq cm and above, increasing stacking-fault densities were found. The oxide defect density associated with time-dependent breakdown increased significantly with Ne dose. The presence of oxidation-expanded defects drastically increases the surface-generation velocity and decreases the bulk lifetime. Slight increases in flatband voltage and surface-state density occurred only for the wafers having the greatest defect concentrations. Oxidation of a P-containing damaged silicon surface results in a greater pileup of P at the surface than occurs for the oxidation of a similar but undamaged surface. It appears that the expanding defects restrain the diffusion of P inward from the surface.

Prussin, S.↗

Quality control during IC processing

Manual gives detailed test procedures for controlling silicon-wafer processing in manufacture of integrated circuits. Included among 43 test procedures are: ionic, bacterial, and solids contamination of high-purity water needed for wafer processing; crystallographic reflection, purity, and orientation; substrate dimensions and finish; thickness of deposited epitaxial films; oxide quality; photoresist characteristics; pinholes in insulating layers; metallized adhesion; and quality of ohmic contact.

Source record↗

CMOS/SOS processing

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Ramondetta, P.↗

Development of improved lithium tantalate pyroelectric detectors

A program was undertaken to increase the detectivity of LiTaO3 pyroelectric detectors to meet a performance requirement of D star (500 K, 15 Hz)=4x10 to the 9th power cm Hz1/2W-1. Emphasis was placed on reduction of the thermal conductance of the detector element to its surroundings, thinning the detector wafer to a thickness less than 3 micrometers, and increasing the absorptivity of the standard metallic film coatings. During the program, thermal conductance was reduced 41 percent through the use of reticulated (slotted) structures. Self-supported detector wafers less than 2 micrometers thick were fabricated. Multiple layer coatings, including an AR coating, with 16 percent more absorptance, were designed and fabricated. Later refinements in the multilayer design program have absorptivities of 75-80 percent, but detectors with these coatings had to be more than 2 micrometers thick because of a mismatch in the thermal expansion coefficients with LiTaO3.

Byer, N. E.↗

Array automated assembly task, phase 2. Low cost silicon solar array project

Several modifications instituted in the wafer surface preparation process served to significantly reduce the process cost to 1.55 cents per peak watt in 1975 cents. Performance verification tests of a laser scanning system showed a limited capability to detect hidden cracks or defects, but with potential equipment modifications this cost effective system could be rendered suitable for applications. Installation of electroless nickel plating system was completed along with an optimization of the wafer plating process. The solder coating and flux removal process verification test was completed. An optimum temperature range of 500-550 C was found to produce uniform solder coating with the restriction that a modified dipping procedure is utilized. Finally, the construction of the spray-on dopant equipment was completed.

Rhee, S. S.↗

Slicing of silicon into sheet material: Silicon sheet growth development for the large area silicon sheet task of the Low Cost Silicon Solar Array project

The limits of blade tolerance were defined. The standard blades are T-2 thickness tolerance. Good results were obtained by using a slurry fluid consisting of mineral oil and a lubricity additive. Adjustments of the formulation and fine tuning of the cutting process with the new fluid are necessary. Test results and consultation indicate that the blade breakage encountered with water based slurries is unavoidable. Two full capacity (974 wafer) runs were made on the large prototype saw. Both runs resulted in extremely low yield. However, the reasons for the low yield were lack of proper technique rather than problems with machine function. The test on the effect of amount of material etched off of an as-sawn wafer on solar cell efficiency were completed. The results agree with previous work at JPL in that the minimum material removed per side that gives maximum efficiency is on the order of 10 microns.

Fleming, J. R.↗

Design, fabrication, and evaluation of charge-coupled devices with aluminum-anodized-aluminum gates

A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.

Gassaway, J. D.↗

Analysis and Evaluation of Processes and Equipment in Tasks 2 and 4 of the Low-cost Solar Array Project

The significant economic data for the current production multiblade wafering and inner diameter slicing processes were tabulated and compared to data on the experimental and projected multiblade slurry, STC ID diamond coated blade, multiwire slurry and crystal systems fixed abrasive multiwire slicing methods. Cost calculations were performed for current production processes and for 1982 and 1986 projected wafering techniques.

Goldman, H.↗

Array Automated Assembly, Phase 2

The baseline process sequence using nontextured square wafers was integrated. Difficulties encountered include: (1) replacement of the N-250 spray on diffusion source with PX-10 source; and (2) modification of the firing for printed silver and aluminum contracts is required to accommodate the change of wafer size and shape. Results indicate that the cells processed through the entire process sequence except laser scribe and spray on AR coating indicate the process sequence is feasible. Greater cell conversion efficiency is presented.

Taylor, W. E.↗

Slicing of Silicon into Sheet Material: Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Silicon Solar Array Project

Testing of low cost low suspension power slurry vehicles is presented. Cutting oils are unlikely to work, but a mineral oil with additives should be workable. Two different abrasives were tested. A cheaper silicon carbide from Norton gave excellent results except for excessive kerf loss: the particles were too big. An abrasive treated for lubricity showed no lubricity improvement in mineral oil vehicle. The bounce fixture was tested for the first time under constant cut rate conditions (rather than constant force). Although the cut was not completed before the blades broke, the blade lifetime of thin (100 micrometer) blades was 120 times the lifetime without the fixture. The large prototype saw completed a successful run, producing 90% cutting yield (849 wafers) at 20 wafers/cm. Although inexperience with large numbers of wafers caused cleaning breakage to reduce this yield to 74%, the yield was high enough that the concept of the large saw is proven workable.

Fleming, J. R.↗

Alternate methods of applying diffusants to silicon solar cells

Low-melting phosphate and borate glasses were screen printed on silicon wafers and heated to form n and p junctions. Data on surface appearance, sheet resistance and junction depth are presented. Similar data are reported for vapor phase transport from sintered aluminum metaphosphate and boron-containing glass-ceramic solid sources. Simultaneous diffusion of an N(+) layer with screen-printed glass and a p(+) layer with screen-printed Al alloy paste was attempted. No p(+) back surface field formation was achieved. Some good cells were produced but the heating in an endless-belt furnace caused a large scatter in sheet resistance and junction depth for three separate lots of wafers.

Brock, T. W.↗

Solar cell with improved N-region contact and method of forming the same

An improved solar cell, and method of forming the same are disclosed. It is characterized by a semiconductor silicon wafer of P-type material having diffused therein a shallow N-type region. A sintered silver contact is affixed to the surface of the N-type region at the outer surface. The improved solar cell is formulated from silver powder blended with silver metaphosphate for establishing a zone of increased carrier concentration. An aluminum or silver-aluminum alloy contact is affixed to the P-type wafer at the outer surface opposite the N-type region.

Bube, K. R.↗

Automated Array Assembly, Phase 2

The large scale production of silicon solar cell array panels is discussed. The cost and performance of three manufacturing sequences designed to convert silicon sheet and wafers into solar panels is analyzed. The production of ion implanted and furnace annealed solar cells made using solar grade n- and p-type wafers is examined. The performance of production size lots is examined with regard to the relationship between the ion implant and furnace anneal parameters and the ability to form consistently good thick film screen printed contacts. The spray on antireflection coating process is evaluated. The performance of several lots of cells before and after coating is measured. The structure and refractive index of the RCA I (TiO2) coating is compared with commercial solutions. Sensitivity of coated, screen printed cells to the post heat treatment required to cure the films is assessed.

Daiello, R. V.↗

A candidate low-cost processing sequence for terrestrial silicon solar cell panel

Manufacturing sequence for silicon solar cells using Czochralsky crystal growing techniques in order to produce at a rate of 20 MW per year on a 24-hour per day basis is discussed. Cost analysis of the manufacturing is presented and consideration is given to the following processing decision categories of the manufacturing of an unencapsulated solar cell from a silicon wafer: (1) treatment of the optical surface; (2) formation of the junction(s); and (3) metallization of electrical collectors. The manufacturing of encapsulated solar modules from solar cells, using two glass plates, a low iron front surface, and a standard float glass back plate, is described. Totaling the three major activities of wafer making, cell manufacturing, and module fabrication, the resulting contribution to module price will be 1.945 $/watt.

Bickler, D. B.↗

Preliminary evaluation of glass resin materials for solar cell cover use

Silicon solar cells and silicon wafers coated with a heat-curable resin consisting of alternating Si-O atoms were subjected to three tests to evaluate the potential utility of this coating in space environments. These included UV irradiation in vacuum at an intensity of 10 air mass zero UV energy-equivalent solar constants for 728 hours followed by a long thermal cycle; 15 thermal shock cycles between 100 C and minus 196 C; and high temperature and humidity (65 C at 90% relative humidity). The UV tests resulted in a 8 to 24% loss in short-circuit current and darkening of the covers. Modification of the resin to provide a better match between the coefficients of expansion of the resin and silicon improved resistance to thermal shock, but also increased the darkening effect under UV irradiation. Silicon wafers coated with the resin were not adversely affected by the temperature/humidity test.

Marsik, S. J.↗

An automated oxide and diffusion facility for IC's

Report discusses totally-automated oxidation and diffusion facility for fabricating IC's. Several innovations are demonstrated: process controller specifically designed for semiconductor processing; automatic loading system to accept wafers from air track, insert them in quartz carrier, and place carrier on paddle for insertion into furnace; automatic unloading of wafers back onto air track; and boron diffusion using diborane.

Kennedy, B. W.↗