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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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The possible processing of semiconductor photovoltaic devices is discussed. The requirements for lunar PV cells is reviewed, and the key challenges involved in their manufacturing are investigated. A schematic diagram of a passivated emitter and rear cell (PERC) is presented. The possible fabrication of large photovoltaic arrays in space from lunar materials is also discussed.
Nonionizing energy loss (NIEL) is a quantity that describes the rate of energy loss due to atomic displacements as a particle traverses a material. The product of the NIEL and the particle fluence (time integrated flux) gives the displacement damage energy deposition per unit mass of material. NIEL plays the same role to the displacement damage energy deposition as the stopping power to the total ionizing dose (TID). The concept of NIEL has been very useful for correlating particle induced displacement damage effects in semiconductor and optical devices. Many studies have successfully demonstrated that the degradation of semiconductor devices or optical sensors in a radiation field can be linearly correlated to the displacement damage energy, and subsequently to the NIEL deposited in the semiconductor devices or optical sensors. In addition, the NIEL concept was also useful in the study of both Si and GaAs solar cells and of high temperature superconductors, and at predicting the survivability of detectors used at the LHC at CERN. On the other hand, there are some instances where discrepancies are observed in the application of NIEL, most notably in GaAs semiconductor devices. However, NIEL is still a valuable tool, and can be used to scale damages produced by different particles and in different environments, even though this is not understood at the microscopic level.
Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Accomplishments include the determination of the reasons for differences in measurements of transistor delay time, identification of an energy level model for gold-doped silicon, and the finding of evidence that it does not appear to be necessary for an ultrasonic bonding tool to grip the wire and move it across the substrate metallization to make the bond. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; measurement of thermal properties of semiconductor devices, delay time, and related carrier transport properties in junction devices, and noise properties of microwave diodes; and characterization of silicon nuclear radiation detectors.
A semiconductor optical device is comprised of a phonon donating material structurally connected to an indirect bandgap material to improve absorption and emission of light in the indirect bandgap material. An excitation energy source provides excitation radiation to the semiconductor optical device to excite electrons in the semiconductor optical device. Phonons from the phonon donating material present in the indirect bandgap material provide a mechanism for increased rates of electron-hole generation and recombination, and electrical leads provide an electrical connection to the semiconductor optical device.
Semiconductor electronic devices and circuits based on silicon carbide (SiC) are being developed for use in high-temperature, high-power, and/or high-radiation conditions under which devices made from conventional semiconductors cannot adequately perform. The ability of SiC-based devices to function under such extreme conditions is expected to enable significant improvements in a variety of applications and systems. These include greatly improved high-voltage switching for saving energy in public electric power distribution and electric motor drives; more powerful microwave electronic circuits for radar and communications; and sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines.
Significant accomplishments include development of a procedure to correct for the substantial differences of transistor delay time as measured with different instruments or with the same instrument at different frequencies; association of infrared response spectra of poor quality germanium gamma ray detectors with spectra of detectors fabricated from portions of a good crystal that had been degraded in known ways; and confirmation of the excellent quality and cosmetic appearance of ultrasonic bonds made with aluminum ribbon wire. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon, development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.
The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
Measurement methods for semiconductor materials, devices, fabrication, processing
This progress report describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices. Significant accomplishments during this reporting period include design of a plan to provide standard silicon wafers for four-probe resistivity measurements for the industry, publication of a summary report on the photoconductive decay method for measuring carrier lifetime, publication of a comprehensive review of the field of wire bond fabrication and testing, and successful completion of organizational activity leading to the establishment of a new group on quality and hardness assurance in ASTM Committee F-1 on Electronics. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers in silicon; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.
Here, we report results of dynamical simulations according to an experimentally validated surface morphological evolution model on the formation of regular arrays of quantum dot molecules (QDMs) consisting of 1D arrays of smaller interacting quantum dots (QDs). These QD arrays form along the sides of each pit rim on the surface of a coherently strained thin film epitaxially deposited on a semiconductor substrate, the surface of which consists of a periodic pattern of inverted prismatic pits with rectangular pit openings. We find that this complex QDM pattern results from the decomposition of the pit rim from a “quantum fortress” with four elongated QDs into four 1D arrays of multiple smaller QDs arranged along each side of the pit rim. Systematic parametric analysis indicates that varying the pit opening dimensions and the pit wall inclination directly impacts the number of QDs in the resulting QDM pattern, while varying the pit depth only affects the dimensions of the QDs in the nanostructure pattern. Therefore, the number, arrangement, and sizes of QDs in the resulting pattern of QDMs on the film surface can be engineered precisely by proper tuning of the pit design parameters. Our simulation results are supported by predictions of morphological stability analysis, which explains the pit rim decomposition into multiple QDs as the outcome of a tip-splitting instability and provides a fundamental characterization of the post-instability nanostructure pattern. Our theoretical findings can play a vital role in designing optimal semiconductor surface patterns toward enabling future nanofabrication technologies.
V-defects are morphological defects that typically form on threading dislocations during epitaxial growth of $(0001)$-oriented GaN layers. A V-defect is a hexagonal pyramid-shaped depression with six {$10\bar{1}1$}-oriented sidewalls. These semipolar sidewalls have a lower polarization barrier than the polarization barriers present between the polar c-plane quantum wells and quantum barriers and can laterally inject carriers directly into quantum wells in GaN-based light emitting diodes (LEDs). This is especially important, as the high polarization field in c-plane GaN is a significant factor in the high forward voltage of GaN LEDs. The optimal V-defect density for efficient lateral carrier injection in a GaN LED (∼10 9 cm −2 ) is typically an order of magnitude higher than the threading dislocation density of GaN grown on patterned sapphire substrates (∼10 8 cm −2 ). Pure-edge dislocation loops have been known to exist in GaN, and their formation into large V-defects via low-temperature growth with high Si-doping has recently been studied. Here, in this work, we develop a method for pure-edge threading dislocation half-loop formation and density control via disilane flow, growth temperature, and thickness of the half-loop generation layer. We also develop a method of forming the threading dislocation half-loops into V-defects of comparable size to those originating from substrate threading dislocations.
Here, the slope efficiency and drive voltage of broad area AlInGaAs laser diodes near 865 nm is observed to decrease significantly under quasi-CW pulsed operation at currents well above threshold, in a manner that cannot be explained by thermal effects or carrier leakage over heterojunction barriers. Simulations show that the slope efficiency reduction is explicable by increased free carrier absorption in the waveguide region. Empirical formulas are presented to represent these effects in a closed analytic form suitable for use in simulators for diode-pumped laser systems.
Semiconductor power devices are typically rated for operation below 150 C. Little data is known for power semiconductors over 150 C. In most cases, the device is derated to zero operating power at 175 C. At the high temperature end of the temperature range, the intrinsic carrier concentration increases to equal the doping concentration level and the silicon behaves as an intrinsic semiconductor. The increase in intrinsic carrier concentration results in a shift of the Fermi level toward mid-bandgap at elevated temperatures. This produces a shift in devices characteristics as a function of temperature. By increasing the doping concentration higher operating temperatures can be achieved. This technique was used to fabricate low power analog and digital devices in silicon with junction operating temperatures in excess of 300 C. Additional temperature effects include increased p-n junction leakage with increasing temperature, resulting in increased resistivity. The temperature dependency of physical properties results in variations in device characteristics. These must be quantified and understood in order to develop extended temperature range operation.
The development of methods of measurement for semiconductor materials, process control, and devices is discussed. The following subjects are also presented: (1) demonstration of the high sensitivity of the infrared response technique by the identification of gold in a germanium diode, (2) verification that transient thermal response is significantly more sensitive to the presence of voids in die attachment than steady-state thermal resistance, and (3) development of equipment for determining susceptibility of transistors to hot spot formation by the current-gain technique.
Hybrid assembly processes for packaging of thin film and semiconductor microelectronic devices
Photovoltaic arrays that convert solar energy into electrical energy can become a cost effective bulk energy generation alternative, provided that an adequate supply of low cost materials is available. One of the key requirements for economic photovoltaic cells is reasonably priced silicon. At present, the photovoltaic industry is dependent upon polycrystalline silicon refined by the Siemens process primarily for integrated circuits, power devices, and discrete semiconductor devices. This dependency is expected to continue until the DOE sponsored low cost silicon refining technology developments have matured to the point where they are in commercial use. The photovoltaic industry can then develop its own source of supply. Silicon material availability and market pricing projections through 1988 are updated based on data collected early in 1984. The silicon refining industry plans to meet the increasing demands of the semiconductor device and photovoltaic product industries are overviewed. In addition, the DOE sponsored technology research for producing low cost polycrystalline silicon, probabilistic cost analysis for the two most promising production processes for achieving the DOE cost goals, and the impacts of the DOE photovoltaics program silicon refining research upon the commercial polycrystalline silicon refining industry are addressed.
Heterogeneous integration techniques allow the coupling of highly lattice-mismatched solid-state membranes, including semiconductors, oxides, and two-dimensional materials, to synergistically fuse the functionalities. The formation of heterostructures generally requires two processes: the combination of crystalline growth and a non-destructive lift-off/transfer process enables the formation of high-quality heterostructures. Although direct atomic interaction between the substrate and the target membrane ensures high-quality growth, the strong atomic bonds at the substrate/epitaxial film interface hinder the non-destructive separation of the target membrane from the substrate. Alternatively, a 2D material-coated compound semiconductor substrate can transfer the weakened (but still effective) surface potential field of the surface through the 2D material, allowing both high-quality epitaxial growth and non-destructive lift-off of the grown film. This Perspective reviews 2D/3D heterogeneous integration techniques, along with applications of III–V compound semiconductors and oxides. Here, the advanced heterogeneous integration methods offer an effective method to produce various freestanding membranes for stackable heterostructures with unique functionalities that can be applied to novel electrical, optoelectronic, neuromorphic, and bioelectronic systems.
In this paper, we use high- and low-magnification optical microscope images, thermal infrared camera images, and scanning electron microscope images to identify failure locations in heavy-ion-irradiated Schottky diodes. After failures have been identified, the parts were cross-sectioned to describe the structure of the failures and energy dispersive x-ray spectroscopy was used to characterize the materials in the failure structures.