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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 595 records · Page 33
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Scalable Circuits for Preparing Ground States on Digital Quantum Computers: The Schwinger Model Vacuum on 100 Qubits

The vacuum of the lattice Schwinger model is prepared on up to 100 qubits of IBM’s Eagle-processor quantum computers. A new algorithm to prepare the ground state of a gapped translationally invariant system on a quantum computer is presented, which we call “scalable circuits ADAPT-VQE” (SC-ADAPT-VQE). This algorithm uses the exponential decay of correlations between distant regions of the ground state, together with ADAPT-VQE, to construct quantum circuits for state preparation that can be scaled to arbitrarily large systems. These scalable circuits can be determined with use of classical computers, avoiding the challenging task of optimizing parameterized circuits on a quantum computer. SC-ADAPT-VQE is applied to the Schwinger model, and is shown to be systematically improvable, with an accuracy that converges exponentially with circuit depth. Both the structure of the circuits and the deviations of prepared wave functions are found to become independent of the number of spatial sites, L . This allows a controlled extrapolation of the circuits, determined with use of small or modest-sized systems, to arbitrarily large L . The circuits for the Schwinger model are determined on lattices up to L = 14 (28 qubits) with the Qiskit classical simulator, and are subsequently scaled up to prepare the L = 50 (100 qubits) vacuum on IBM’s 127-superconducting-qubit quantum computers ibm_brisbane and ibm_cusco. After introduction of an improved error-mitigation technique, which we call “operator decoherence renormalization”, the chiral condensate and charge-charge correlators obtained from the quantum computers are found to be in good agreement with classical matrix product state simulations. Published by the American Physical Society 2024

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Native Two-Qubit Gates in Fixed-Coupling, Fixed-Frequency Transmons Beyond Cross-Resonance Interaction

Fixed-frequency superconducting qubits demonstrate remarkable success as platforms for stable and scalable quantum computing. Cross-resonance gates have been the workhorse of fixed-coupling, fixed-frequency superconducting processors, leveraging the entanglement generated by driving one qubit resonantly with a neighbor’s frequency to achieve high-fidelity, universal controlled- () gates. Here, we use on-resonant and off-resonant microwave drives to go beyond cross-resonance, realizing natively interesting two-qubit gates that are not equivalent to gates. In particular, we implement and benchmark native i , , i SWAP , and b gates; in fact, any SU ( 4 ) unitary can be achieved using these techniques. Furthermore, we apply these techniques for an efficient construction of the B gate: a perfect entangler from which any two-qubit gate can be reached in only two applications. We show that these native two-qubit gates are better than their counterparts compiled from cross-resonance gates. We elucidate the resonance conditions required to drive each two-qubit gate and provide a novel frame tracking technique to implement them in Qiskit. Published by the American Physical Society 2024

Physics↗
DOE OSTI2024

Dynamic Cooling on Contemporary Quantum Computers

We study the problem of dynamic cooling whereby a target qubit is cooled at the expense of heating up N − 1 further identical qubits by means of a global unitary operation. A standard back-of-the-envelope high-temperature estimate establishes that the target qubit temperature can be dynamically cooled by at most a factor of 1 / N . Here we provide the exact expression for the minimum temperature to which the target qubit can be cooled and reveal that there is a crossover from the high initial temperature regime, where the scaling is 1 / N , to a low initial temperature regime, where a much faster scaling of 1 / N occurs. This slow, 1 / N scaling, which was relevant for early high-temperature NMR quantum computers, is the reason dynamic cooling was dismissed as ineffectual around 20 years ago; the fact that current low-temperature quantum computers fall in the fast, 1 / N scaling regime, reinstates the appeal of dynamic cooling today. We further show that the associated work cost of cooling is exponentially more advantageous in the low-temperature regime. We discuss the implementation of dynamic cooling in terms of quantum circuits and examine the effects of hardware noise. We successfully demonstrate dynamic cooling in a three-qubit system on a real quantum processor. Since the circuit size grows quickly with N , scaling dynamic cooling to larger systems on noisy devices poses a challenge. We therefore propose a suboptimal cooling algorithm, whereby relinquishing a small amount of cooling capability results in a drastically reduced circuit complexity, greatly facilitating the implementation of dynamic cooling on near-future quantum computers. Published by the American Physical Society2024

Physics↗
DOE OSTI2024

Superconducting Qubits above 20 GHz Operating over 200 mK

Current state-of-the-art superconducting microwave qubits are cooled to extremely low temperatures to avoid sources of decoherence. Higher qubit operating temperatures would significantly increase the cooling power available, which is desirable for scaling up the number of qubits in quantum computing architectures and integrating qubits in experiments requiring increased heat dissipation. To operate superconducting qubits at higher temperatures, it is necessary to address both quasiparticle decoherence (which becomes significant for aluminum junctions above 160 mK) and dephasing from thermal microwave photons (which are problematic above 50 mK). Using low-loss niobium-trilayer junctions, which have reduced sensitivity to quasiparticles due to the higher superconducting transition temperature of niobium, we fabricate transmons with higher frequencies than previously studied, up to 24 GHz. We measure decoherence and dephasing times of about 1 μs, corresponding to average qubit quality factors of approximately 10 5 , and find that decoherence is unaffected by quasiparticles up to 1 K. Without relaxation from quasiparticles, we are able to explore dephasing from purely thermal sources, finding that our qubits can operate up to approximately 250 mK while maintaining similar performance. The thermal resilience of these qubits creates new options for scaling up quantum processors, enables hybrid quantum experiments with high heat-dissipation budgets, and introduces a material platform for even-higher-frequency qubits.

Josephson junctions↗
DOE OSTI2025

Offset Charge Dependence of Measurement-Induced Transitions in Transmons

A key challenge in achieving scalable fault tolerance in superconducting quantum processors is readout fidelity, which lags behind one- and two-qubit gate fidelity. A major limitation in improving qubit readout is measurement-induced transitions, also referred to as qubit ionization, caused by multiphoton qubit-resonator excitation occurring at specific photon numbers. Since ionization can involve highly excited states, it has been predicted that in transmons—the most widely used superconducting qubit—the photon number at which measurement-induced transitions occur is gate-charge dependent. This dependence is expected to persist deep in the transmon regime where the qubit frequency is gate-charge insensitive. We experimentally confirm this prediction by characterizing measurement-induced transitions with increasing resonator photon population while actively calibrating the transmon’s gate charge. Furthermore, because highly excited states are involved, achieving quantitative agreement between theory and experiment requires accounting for higher-order harmonics in the transmon Hamiltonian.

Quantum circuits↗
DOE OSTI2023

Genetic Algorithm-Based Commutation Angle Control for Torque Ripple Mitigation in Switched Reluctance Motor Drives

This work addresses the application of the Genetic Algorithm (GA) technique to optimize the commutation angles of a 2 kW 8/6 switched reluctance machine (SRM). The primary goal is to reduce the well-known drawback of SRMs: the torque ripple. Firstly, the machine was modeled in Matlab /Simulink ® using lookup tables obtained via finite element method (FEM) simulations. Subsequently, the model was used to perform the GA routine aiming to find the optimal phase commutation angles that minimize the torque ripple factor. Notably, the torque performance of the SRM was significantly affected by the commutation angles during the search for the optimal solution. Afterwards, the GA results for four different operation points were verified experimentally through a developed drive platform with digital signal processor-based (DSP) control and an asymmetric bridge converter. As showed by the experiments, the proposed approach was suitable to reduce the torque ripple by more than 50% for one of the evaluated operating points. Furthermore, it was confirmed that the torque ripple mitigation led to acoustic noise improvement.

42 ENGINEERING↗
DOE OSTI2021

A Novel Decentralized PWM Interleaving Technique for Ripple Minimization in Series-Stacked DC-DC Converters

Cascaded dc-dc converters are commonly used in applications where distributed energy sources or loads are connected to elevated voltage levels for power transfer. In such systems, it is advantageous to minimize the ripple on the bus current and voltage by proper phase shifting of the pulse-width modulation (PWM) pulses among the converters via a method known as interleaving. Existing approaches use either a centralized controller or separate communication lines among the stacked converters to control their relative PWM switch transitions. The key drawbacks are that these methods entail significant wiring, the central controller acts as a single point of failure, and implementation on very large numbers of units is impractical. In this paper, we introduce a decentralized interleaving control (DIC) strategy that acts on local current measurements at every converter and achieves communication-free PWM interleaving among the series-stacked converters. The proposed controller is simple in structure and is shown to converge asymptotically to the interleaved state irrespective of clock drifts among the digital signal processors. Experimental results are provided for a system of five series-connected converters showing a 10× reduction in the current ripple compared to normal operation.

cascaded converter↗
DOE OSTI2023

Open Circuit Switch Fault Management Method of a Multi-Phase Synchronous Buck Converter for EV Charging Application

Multi-phase synchronous buck converter (MSBC) is becoming popular for the electric vehicle (EV) charging application because of its higher efficiency, smaller passive component sizes, bidirectional power flow, and output current ripple reduction through interleaving. This converter also provides higher reliability than the traditional single phase converter since its modular structure enables fault tolerant operation. Fault management in the converter requires the detection of switch fault, shut down of the faulty phase, and reconfiguration of the PWM signals for the healthy phases to avoid circulating current and high output current ripple. In addition, it is desirable that the fault management method can be implemented using the micro-controller unit (MCU) or digital signal processor (DSP), which are widely used to control power converters. This paper presents a fault management method for detecting switch faults and reconfiguring healthy phases using a DSP. The method is validated through simulations and experiments using a commercial off-the-shelf power stack.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Architecture for Quantum-in-the Loop Real-Time Simulations for Designing Resilient Smart Grids

With the power grid growing more complex every day with the inclusion of new sensors and regulatory approvals that enable end-users and small local developers to participate in the grid, it is becoming challenging for conventional smart grid simulation, emulation, and testing technologies to keep up. In this work, we propose that quantum-encoded real-time simulations can be helpful under the new paradigm and operational circumstances to solve optimization problems for power grids. By leveraging the principles of quantum mechanics, the proposed quantum-in-loop (QIL) framework will enable better and faster optimization solutions based on real-world, real-time data streams, facilitating the real-time planning and operations of electrical grids that rely on millions of distributed sensors and controllers. Furthermore, QIL will allow researchers and engineers to assist utilities in designing, developing, and de-risking algorithms to optimize power grid operation and resilience by considering inputs from millions of grid-connected devices. QIL framework is being developed to have a self-limiting triage mechanism, which will help engineers and practitioners identify fundamental physical limits on quantum processors, revealing what quantum algorithms can and cannot do in utility-specific use cases and must continue to count on classical high-performance computing infrastructure.

digital real-time simulation↗
DOE OSTI2022

MemGaze: Rapid and Effective Load-Level Memory Trace Analysis

A major challenge of memory analysis tools is combining high-resolution analysis and low overhead measurement. Currently, hardware/software-based analysis of load-level sequences incurs time slowdowns of O(100×). We present MemGaze, a tool for low-overhead, high-resolution memory analysis. MemGaze uses Intel’s Processor Tracing (PT) instruction ptwrite to collect sampled and compressed memory address traces for load-level, sequence-aware analysis of data reuse. We describe multi-resolution analysis for locations vs. operations, accesses vs. spatio-temporal reuse, and reuse (distance, rate, volume) vs. access patterns. Both trace size and resolution are controllable. We use MemGaze to elucidate the memory effects of different data structures and algorithms. For sampled traces that are ˜1% of a full one, analysis metrics have 1-25% MAPE for histograms of varying dynamic sequence lengths. With current suboptimal kernel support (PT runs continuously), MemGaze’s time overhead is typically 10–95%; 7× at worst. However, when PT runs only during samples, overhead is 10–35% on memory intensive regions and correlates with executed ptwrites.

Kilic, Ozgur O.↗
DOE OSTI2023

ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs

Coarse-Grained Reconfigurable Arrays (CGRAs) can achieve higher energy-efficiency than general-purpose processors and accelerators or fine-grained reconfigurable devices, while maintaining adaptability to different computational patterns. CGRAs have shown some success as a platform to accelerate machine learning (ML) thanks to their flexibility, which allows them to support new models not considered by fixed accelerators. However, current solutions for CGRAs employ low level instruction-based compiler approaches and lack specialized compilation infrastructures from high-level ML frameworks that could leverage semantic information from the models, limiting the ability to efficiently map them on the recon- figurable substrate. This paper proposes ML-CGRA, an integrated compilation framework based on the MLIR infrastructure that en- ables efficient ML acceleration on CGRAs. ML-CGRA provides an end-to-end solution for mapping ML models on CGRAs that out- performs conventional approaches by 3.15× and 6.02 × on 4×4 and 8×8 CGRAs, respectively.

machine learning↗
DOE OSTI2021

Multi-Core Microcontroller Hardware In the Loop System for Electric Machine Control

Hardware in the Loop (HIL) is a simulation technique used to reduce the software development cycle and test control systems in a non-destructive environment. This work describes a cost effective HIL simulator on a dual core microcontroller in which one core acts as a controller and the other emulates the system under control. The emulator runs one step per Pulse Width Modulation (PWM) period in real time. To handle the computational burden and prioritize execution of simulation and control tasks, an interrupt-based software architecture with task prioritization has been developed. As a demonstration, the HIL has been implemented on a Texas Instruments TMS320F28379D dual core microcontroller, which emulates a Permanent Magnet Synchronous Machine (PMSM) with resolver feedback. Hardware peripherals are developed and tested concurrently with the control system, providing higher confidence in the software. By using the peripherals in the HIL development, the controller exercises either the HIL emulation or a pin compatible PMSM testbench. To quantify performance and validate the processor based emulator, the HIL results are compared to the preexisting testbench for accuracy benchmarking at no-load and under load for a range of operating points.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2022

Power Electronic Hardware-in-the-Loop (PE-HIL): Testing Individual Controllers in Large-Scale Power Electronics Systems

Large power electronics systems like multi-port autonomous reconfigurable solar power plant (MARS) are increasingly being researched upon to integrate emerging energy sources. MARS connects photovoltaic (PV) systems and energy storage systems (ESSs) to high-voltage direct current (HVdc) links/grids and high-voltage alternating current (ac) transmission grids. As these large power electronics systems incorporate complex hierarchical control systems that are close-by and communicate fast, the control systems require an unique power electronic hardware-in-the-loop (PE-HIL) real-time architecture to evaluate individual controllers. In this paper, a PE-HIL real-time architecture is proposed to evaluate one of the hundreds to thousands of digital signal processors (DSPs) that are a part of the complex hierarchical control system. The DSP connects to a central processing unit (CPU) and a field programmable gate array (FPGA) that form a part of the upper levels of the control system. The DSP is part of the lower level of the control system. The proposed PE-HIL architecture is tested and evaluated. Preliminary test results are presented to showcase the concept.

Debnath, Suman↗
DOE OSTI2023

A Robust Method to Secure Multi-Inverter Grid Tied PV and Battery Energy Storage Systems Against Cyber Intrusions

This paper details a robust method to secure a multi-inverter grid tied system that interfaces photovoltaic (PV) and battery energy storage against potential cyber-attacks. The method can be applied to any third-party inverter systems without a need to modify their internal controls. A small random private excitation signal termed "watermark" is injected into the DC input voltage terminals (via a series transformer) connected to the PV/battery inverter system. An external robust cyber intrusion detector (CID) hardware consisting of a digital signal processor (DSP) generates the "watermark" and also receives the sensor signals that control the setpoints of the PV/battery grid tied system. The CID algorithm is shown to detect all possible cyber intrusions (such as false data injection(FDI)) on external sensor signals such as P and Q measured by a smart meter that control the overall system operation. The proposed CID computes online system ID and two variance tests in real time on each sensor signal and is able pinpoint intrusion location in a multi-inverter system. Results on a hardware in the loop (HIL) of a two-inverter grid connected system demonstrate effectiveness of the proposed CID system for FDI and unobservable FDI. Test results on a laboratory prototype will be discussed in the conference presentation.

Ibrahim, Hasan↗
DOE OSTI2021

Educating HPC Users in the use of advanced computing technology

We examine a multi-modal approach to educating and training users of an advanced computing technology testbed at the Institute for Advanced Computational Science at Stony Brook University. Ookami provides researchers worldwide with access to 176 Fujitsu A64FX compute nodes, this being the same processor technology powering the Japanese Fugaku supercomputer, the fastest computer in the world since June 2020. However, achieving high-performance on this Arm-based, leadership computing technology requires that users be familiar with details of computer architecture, performance analysis and modeling, and high-performance programming models that are commonly omitted in introductory programming courses. Indeed, regardless of their seniority, many of the testbed users are surprisingly unfamiliar with basic concepts such as vectorization, pipelining, latency/bandwidth, roofline models, computing energy/power, threads, and non-uniform memory access. These same concepts also pervade mainstream x86 technologies, so this is of widespread concern. Due to the national/global nature of our user community that is also very diverse in both discipline and experience, the inability to offer formal classes, and our experience that most people do not tend to read online documentation or training materials in sufficient depth, we have consciously employed multiple approaches that heavily emphasize (online) personal interactions and transfer of skills. Online documentation has been organized around best-practices and FAQs; twice-weekly hackathons and office hours via Zoom enable deep dives by both the team and the user community with multiple broad benefits; a Slack channel provides both real time and archived answers and discussions; and workshops, training and webinars target community needs as they arise. Furthermore, the perspective that these tools are being used in an educational setting rather than just for project communication makes them more effective and contributes to community success.

A64FX↗
DOE OSTI2021

Elastic distributed training with fast convergence and efficient resource utilization

Distributed learning is now routinely conducted on cloud as well as dedicated clusters. Training with elastic resources brings new challenges and design choices. Prior studies focus on runtime performance and assume a static algorithmic behavior. In this work, by analyzing the impact of of resource scaling on convergence, we introduce schedules for synchronous stochastic gradient descent that proactively adapt the number of learners to reduce training time and improve convergence. Our approach no longer assumes a constant number of processors throughout training. In our experiment, distributed stochastic gradient descent with dynamic schedules and reduction momentum achieves better convergence and significant speedups over prior static ones. Numerous distributed training jobs running on cloud may benefit from our approach.

Cong, Guojing↗
DOE OSTI2025

Virtual Cable Impedance based Load Sharing in a Microgrid for Parallel Connected Grid Forming Converters

This paper presents a novel approach to power sharing between direct connected grid-forming converters, utilizing virtual cable impedance and droop-based outer loop control. To enhance stability, resistive droop is implemented, while virtual cable impedance with non-zero resistive and inductive components ensures improved power sharing. The inner loop controller employs a Lyapunov energy function to achieve superior dynamic performance. The proposed control architecture is validated through comprehensive modeling and real-time processor-in-the-loop simulations, demonstrating its robustness and efficiency under various operating conditions. The results highlight the potential of this control strategy to improve the reliability and efficiency of renewable energy systems. Additionally, a comparative analysis with traditional methods underscores the advantages of the proposed approach in terms of stability and performance. The proposed control architecture offers a scalable and flexible solution for grid-forming converters, enabling seamless integration of renewable energy sources. Its robustness and adaptability make it an attractive solution for real-world applications. Furthermore, the approach can be extended to other power electronic systems, enhancing overall system performance and efficiency. By providing a reliable and efficient control strategy, this paper contributes to the advancement of renewable energy systems and their adoption in the energy sector. The proposed control strategy has far-reaching implications for the widespread adoption of renewable energy sources, enabling a more sustainable and efficient energy future. The overall system is modeled in MATLAB/Simulink and PLECS software domain.

grid forming converters (GFM)↗
DOE OSTI2020

Scaled-up Neuromorphic Array Communications Controller (SNACC) for Large-scale Neural Networks

Neuromorphic computing is one promising post-Moore’s law era technology, which takes inspiration from biological brains to perform computing tasks. The human brain contains billions of neurons with trillions of synapses and as neuromorphic hardware systems scale to larger and larger sizes, the communication system used to transfer information between neuromorphic elements and traditional computers must scale to keep up. In prior work, we describe the use of a separate neuromorphic array communications controller to support low-latency, high-throughput communication between our neuromorphic systems and a traditional computer. In this work, the neuromorphic array communications controller is used to support the scaling of a neuromorphic development system which uses multiple neuromorphic processors arranged in a two-dimensional array. The neuromorphic array communications controller, along with scalable local connections, is used to create a scalable neuromorphic platform to enable the development and testing of large neuromorphic network arrays.

Young, Aaron↗