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At least 595 records · Page 33

All sources NASA NTRS DOE OSTI

NASA NTRS2015

An Efficient Solution Method for Multibody Systems with Loops Using Multiple Processors

This paper describes a multibody dynamics algorithm formulated for parallel implementation on multiprocessor computing platforms using the divide-and-conquer approach. The system of interest is a general topology of rigid and elastic articulated bodies with or without loops. The algorithm divides the multibody system into a number of smaller sets of bodies in chain or tree structures, called "branches" at convenient joints called "connection points", and uses an Order-N (O (N)) approach to formulate the dynamics of each branch in terms of the unknown spatial connection forces. The equations of motion for the branches, leaving the connection forces as unknowns, are implemented in separate processors in parallel for computational efficiency, and the equations for all the unknown connection forces are synthesized and solved in one or several processors. The performances of two implementations of this divide-and-conquer algorithm in multiple processors are compared with an existing method implemented on a single processor.

Multibody dynamics↗

NASA NTRS2017

Open-Source RTOS Space Qualification: An RTEMS Case Study

NASA space-qualification of reusable off-the-shelf real-time operating systems (RTOSs) remains elusive due to several factors notably (1) The diverse nature of RTOSs utilized across NASA, (2) No single NASA space-qualification criteria, lack of verification and validation (V&V) analysis, or test beds, and (3) different RTOS heritages, specifically open-source RTOSs and closed vendor-provided RTOSs. As a leader in simulation test beds, the NASA IV&V Program is poised to help jump-start and lead the space-qualification effort of the open source Real-Time Executive for Multiprocessor Systems (RTEMS) RTOS. RTEMS, as a case-study, can be utilized as an example of how to qualify all RTOSs, particularly the reusable non-commercial (open-source) ones that are gaining usage and popularity across NASA. Qualification will improve the overall safety and mission assurance of RTOSs for NASA-agency wide usage. NASA's involvement in space-qualification of an open-source RTOS such as RTEMS will drive the RTOS industry toward a more qualified and mature open-source RTOS product.

Real-time operating system↗

NASA NTRS2010

NASA Accelerates SpaceCube Technology into Orbit

On May 11, 2009, STS-125 Space Shuttle Atlantis blasted off from Kennedy Space Center on a historic mission to service the Hubble Space Telescope (HST). In addition to sending up the hardware and tools required to repair the observatory, the servicing team at NASA's Goddard Space Flight Center also sent along a complex experimental payload called Relative Navigation Sensors (RNS). The main objective of the RNS payload was to provide real-time image tracking of HST during rendezvous and docking operations. RNS was a complete success, and was brought to life by four Xilinx FPGAs (Field Programmable Gate Arrays) tightly packed into one integrated computer called SpaceCube. SpaceCube is a compact, reconfigurable, multiprocessor computing platform for space applications demanding extreme processing capabilities based on Xilinx Virtex 4 FX60 FPGAs. In a matter of months, the concept quickly went from the white board to a fully funded flight project. The 4-inch by 4-inch SpaceCube processor card was prototyped by a group of Goddard engineers using internal research funding. Once engineers were able to demonstrate the processing power of SpaceCube to NASA, HST management stood behind the product and invested in a flight qualified version, inserting it into the heart of the RNS system. With the determination of putting Xilinx into space, the team strengthened to a small army and delivered a fully functional, space qualified system to the mission.

Petrick, David↗

NASA NTRS2001

Highly parallel structured adaptive mesh refinement using parallel language-based approaches

Adaptive mesh refinement (AMR) calculations carried out on structured meshes play an exceedingly important role in several areas of science and engineering. A strategy for using Fortran 90 in an object-oriented fashion is presented. This permits AMR applications to be expressed in terms of familiar abstractions that are natural to the process of solving AMR hierarchies. The OpenMP features that are useful for parallel processing of AMR hierarchies in a load balanced fashion on multiprocessors is described.

computational↗

NASA NTRS2022

The Harmonic Linearized Navier-Stokes Equations for Transition Prediction in Three-Dimensional Flows

The conventional method to predict the onset of laminar-turbulent transition in convectively unstable boundary-layer flows is based on the logarithmic amplification ratio, the so-called N-factor, of the linear instability waves. To calculate the N-factor, the flow variables are decomposed into a laminar basic state solution and the linear disturbances, which are assumed to be harmonic in time. The most commonly used linear stability analysis approaches include the locally parallel linear stability theory (LST) and the nonlocal, weakly nonparallel parabolized stability equations (PSE). However, these methods do not account for strong streamwise gradients that are encountered in several configurations of interest, such as those in the vicinity of roughness elements, steps, gaps, or corners. To compute the linear evolution of disturbances along such strongly nonparallel regions, the harmonic linearized Navier-Stokes equations (HLNSE) need to be solved. The discretization of the HLNSE for spanwise/azimuthally inhomogeneous laminar basic states yields a linear system of complex arithmetic with a leading dimension of the order of 10^(7) to 10^(8) even in relatively simple flows. A combined multithread and multiprocessor algorithm is implemented for the direct solution of such linear systems. Results for a supersonic boundary layer over a three-dimensional roughness patch show good agreement with experimental measurements when the evolution of the instability waves over the roughness patch is included via the HLNSE. Additionally, inflow-resolvent analysis based on the HLNSE for discrete-roughness-induced disturbances in the nose tip of a blunt cone at Mach 6 demonstrates the importance of including the disturbance amplification along the near vicinity of the roughness element and separation region.

Boundary Layer Stability↗

NASA NTRS2022

The Harmonic Linearized Navier-Stokes Equations for Transition Prediction in Three-Dimensional Flows

The conventional method to predict the onset of laminar-turbulent transition in convectively unstable boundary-layer flows is based on the logarithmic amplification ratio, the so-called N-factor, of the linear instability waves. To calculate the N-factor, the flow variables are decomposed into a laminar basic state solution and the linear disturbances, which are assumed to be harmonic in time. The most commonly used linear stability analysis approaches include the locally parallel linear stability theory (LST) and the non-local, weakly nonparallel parabolized stability equations (PSE). However, these methods do not account for strong streamwise gradients that are encountered in several configurations of interest, as roughness elements, steps, gaps, or corners. To solve the linear evolution of disturbances along such strongly nonparallel regions, the harmonic linearized Navier-Stokes equations (HLNSE) need to be solved. The discretization of the HLNSE for spanwise/azimuthally inhomogeneous laminar basic states yields a linear system of complex arithmetic with a leading dimension of the order of 107 to 108. A combined multithread and multiprocessor algorithm is implemented for the direct solution of such linear system. Results for a supersonic boundary layer over a three-dimensional roughness patch show good agreement with experimental measurements when the evolution of the instability waves over the roughness patch is included via the HLNSE.

Boundary Layer Stability↗

NASA NTRSDate not supplied

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

heterogeneous processing system↗

NASA NTRSDate not supplied

Safe and Precise Landing Integrated Capabilities Evolution (SPLICE)

NASA needs for entry, descent, and landing call for improved Precision Landing and Hazard Avoidance (PL&HA) technologies. SPLICE continues to develop, mature, demonstrate, and infuse these technologies as a portfolio. SPLICE will achieve TRL 5 on a hazard detection lidar mapping sensor and TRL 6 on two key flight software libraries for advanced guidance and hazard detection. A High-Performance Space Computing surrogate multiprocessor (ARM A53) integrates sensors and FSW. This portfolio of technologies may be infused separately or fully integrated.

Guidance Navigation and Control↗

NASA NTRS2023

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

David K. Rutishauser↗

DOE OSTI2013

Cache directory look-up re-use as conflict check mechanism for speculative memory requests

In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory lookups serving as the point of conflict detection, such saving becomes particularly advantageous.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2014

Method and apparatus for efficiently tracking queue entries relative to a timestamp

An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2014

Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2014

Cache directory lookup reader set encoding for partial cache line speculation support

In a multiprocessor system, with conflict checking implemented in a directory lookup of a shared cache memory, a reader set encoding permits dynamic recordation of read accesses. The reader set encoding includes an indication of a portion of a line read, for instance by indicating boundaries of read accesses. Different encodings may apply to different types of speculative execution.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

A Framework for Batched and GPU-Resident Factorization Algorithms Applied to Block Householder Transformations

As modern hardware keeps evolving, an increasingly effective approach to developing energy efficient and high-performance solvers is to design them to work on many small size and independent problems. Many applications already need this functionality, especially for GPUs, which are currently known to be about four to five times more energy efficient than multicore CPUs. We describe the development of one-sided factorizations that work for a set of small dense matrices in parallel, and we illustrate our techniques on the QR factorization based on Householder transformations. We refer to this mode of operation as a batched factorization. Our approach is based on representing the algorithms as a sequence of batched BLAS routines for GPU-only execution. This is in contrast to the hybrid CPU-GPU algorithms that rely heavily on using the multicore CPU for specific parts of the workload. But for a system to benefit fully from the GPU's significantly higher energy efficiency, avoiding the use of the multicore CPU must be a primary design goal, so the system can rely more heavily on the more efficient GPU. Additionally, this will result in the removal of the costly CPU-to-GPU communication. Furthermore, we do not use a single symmetric multiprocessor(on the GPU) to factorize a single problem at a time. We illustrate how our performance analysis, and the use of profiling and tracing tools, guided the development and optimization of our batched factorization to achieve up to a 2-fold speedup and a 3-fold energy efficiency improvement compared to our highly optimized batched CPU implementations based on the MKL library(when using two sockets of Intel Sandy Bridge CPUs). Compared to a batched QR factorization featured in the CUBLAS library for GPUs, we achieved up to 5x speedup on the K40 GPU.

Dong, Tingzing Tim↗

DOE OSTI2013

A Latency Tolerant Runtime System for Mass Market Computer Systems

Grappa is a latency tolerant runtime system for mass market computer systems comprised of multiple nodes having x86 multicore processors and infiniband interconnect. Grappa is designed to enable in-memory irregular applications written in the C++ programming language to scale up on multiprocessor systems. Grappa addresses the load balance, communication, and synchronization challenges posed by running applications that do not partition evenly across large systems. Two mechanisms are essential to its success: fast task switching and message aggregation. Fast task switching enables processors to tolerate communication and synchronization delays; aggregation sustains high bandwidth on low injection rate networks.

Source record↗

DOE OSTI2018

Single-pass parallel prefix scan with dynamic look back

One embodiment of the present invention performs a parallel prefix scan in a single pass that incorporates variable look-back. A parallel processing unit (PPU) subdivides a list of inputs into sequentially-ordered segments and assigns each segment to a streaming multiprocessor (SM) included in the PPU. Notably, the SMs may operate in parallel. Each SM executes write operations on a segment descriptor that includes the status, aggregate, and inclusive-prefix associated with the assigned segment. Further, each SM may execute read operations on segment descriptors associated with other segments. In operation, each SM may perform reduction operations to determine a segment-wide aggregate, may perform look-back operations across multiple preceding segments to determine an exclusive-prefix, and may perform a scan seeded with the exclusive prefix to generate output data. Advantageously, the PPU performs one read operation per input, thereby reducing the time required to execute the prefix scan relative to prior-art parallel implementations.

Merrill, Duane↗

DOE OSTI2023

Computing rank‐revealing factorizations of matrices stored out‐of‐core

This paper describes efficient algorithms for computing rank-revealing factorizations of matrices that are too large to fit in main memory (RAM), and must instead be stored on slow external memory devices such as disks (out-of-core or out-of-memory). Traditional algorithms for computing rank-revealing factorizations (such as the column pivoted QR factorization and the singular value decomposition) are very communication intensive as they require many vector-vector and matrix-vector operations, which become prohibitively expensive when data is not in RAM. Randomization allows to reformulate new methods so that large contiguous blocks of the matrix are processed in bulk. The paper describes two distinct methods. The first is a blocked version of column pivoted Householder QR, organized as a “left-looking” method to minimize the number of the expensive write operations. The second method results employs a UTV factorization. It is organized as an algorithm-by-blocks to overlap computations and I/O operations. As it incorporates power iterations, it is much better at revealing the numerical rank. Numerical experiments on several computers demonstrate that the new algorithms are almost as fast when processing data stored on slow memory devices as traditional algorithms are for data stored in RAM.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2016

Performance Models for Split-execution Computing Systems

Split-execution computing leverages the capabilities of multiple computational models to solve problems, but splitting program execution across different computational models incurs costs associated with the translation between domains. We analyze the performance of a split-execution computing system developed from conventional and quantum processing units (QPUs) by using behavioral models that track resource usage. We focus on asymmetric processing models built using conventional CPUs and a family of special-purpose QPUs that employ quantum computing principles. Our performance models account for the translation of a classical optimization problem into the physical representation required by the quantum processor while also accounting for hardware limitations and conventional processor speed and memory. We conclude that the bottleneck in this split-execution computing system lies at the quantum-classical interface and that the primary time cost is independent of quantum processor behavior.

multiprocessor↗