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At least 595 records · Page 33

All sources NASA NTRS DOE OSTI

DOE OSTI2014

Low power ovonic threshold switching characteristics of thin GeTe{sub 6} films using conductive atomic force microscopy

Minimizing the dimensions of the electrode could directly impact the energy-efficient threshold switching and programming characteristics of phase change memory devices. A ∼12–15 nm AFM probe-tip was employed as one of the electrodes for a systematic study of threshold switching of as-deposited amorphous GeTe{sub 6} thin films. This configuration enables low power threshold switching with an extremely low steady state current in the on state of 6–8 nA. Analysis of over 48 different probe locations on the sample reveals a stable Ovonic threshold switching behavior at threshold voltage, V{sub TH} of 2.4 ± 0.5 V and the off state was retained below a holding voltage, V{sub H} of 0.6 ± 0.1 V. All these probe locations exhibit repeatable on-off transitions for more than 175 pulses at each location. Furthermore, by utilizing longer biasing voltages while scanning, a plausible nano-scale control over the phase change behavior from as-deposited amorphous to crystalline phase was studied.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2026

Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.

FOS: Physical sciences↗

DOE OSTI2015

Gregarious Data Re-structuring in a Many Core Architecture

this paper, we have developed a new methodology that takes in consideration the access patterns from a single parallel actor (e.g. a thread), as well as, the access patterns of “grouped” parallel actors that share a resource (e.g. a distributed Level 3 cache). We start with a hierarchical tile code for our target machine and apply a series of transformations at the tile level to improve data residence in a given memory hierarchy level. The contribution of this paper includes (a) collaborative data restructuring for group reuse and (b) low overhead transformation technique to improve access pattern and bring closely connected data elements together. Preliminary results in a many core architecture, Tilera TileGX, shows promising improvements over optimized OpenMP code (up to 31% increase in GFLOPS) and over our own previous work on fine grained runtimes (up to 16%) for selected kernels

data restructuring↗

NASA NTRS2003

SpaceWire Driver Software for Special DSPs

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Clark, Douglas↗

DOE OSTI2020

Ionic complexation of endblock-sulfonated thermoplastic elastomers and their physical gels for improved thermomechanical performance

Thermoplastic elastomers (TPEs) composed of nonpolar triblock copolymers constitute a broadly important class of (re)processable network-forming macromolecules employed in ubiquitous commercial applications. Physical gelation of these materials in the presence of a low-volatility oil that is midblock-selective yields tunably soft TPE gels (TPEGs) that are suitable for emergent technologies ranging from electroactive, phase-change and shape-memory responsive media to patternable soft substrates for flexible electronics and microfluidics. Many of the high-volume TPEs used for these purposes possess styrenic endblocks that are inherently limited by a relatively low glass transition temperature. To mitigate this shortcoming, we sulfonate and subsequently complex (and physically crosslink) the endblocks with trivalent Al3+ ions. Doing so reduces the effective hydrophilicity of the sulfonated endblocks, as evidenced by water uptake measurements, while concurrently enhancing the thermomechanical stability of the corresponding TPEGs. Chemical modification results, as well as morphological and property development, are investigated as functions of the degree of sulfonation, complexation and TPEG composition. (C) 2020 Published by Elsevier Inc.

36 MATERIALS SCIENCE↗

DOE OSTI2014

Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2014

Shape-memory transformations of NiTi: Minimum-energy pathways between austenite, martensites, and kinetically limited intermediate states

NiTi is the most used shape-memory alloy, nonetheless, a lack of understanding remains regarding the associated structures and transitions, including their barriers. Using a generalized solid-state nudge elastic band (GSSNEB) method implemented via density-functional theory, we detail the structural transformations in NiTi relevant to shape memory: those between body-centered orthorhombic (BCO) groundstate and a newly identified stable austenite (“glassy” B2-like) structure, including energy barriers (hysteresis) and intermediate structures (observed as a kinetically limited R-phase), and between martensite variants (BCO orientations). All results are in good agreement with available experiment. We contrast the austenite results to those from the often-assumed, but unstable B2. Furthermore, these high- and low-temperature structures and structural transformations provide much needed atomic-scale detail for transitions responsible for NiTi shape-memory effects.

36 MATERIALS SCIENCE↗

DOE OSTI2014

Nanosecond switching in GeSe phase change memory films by atomic force microscopy

Nanosecond scale threshold switching is investigated with conducting atomic force microscopy (AFM) for an amorphous GeSe film. Switched bits exhibit 2–3 orders of magnitude variations in conductivity, as demonstrated in phase change based memory devices. Through the nm-scale AFM probe, this crystallization was achieved with pulse durations of as low as 15 ns, the fastest reported with scanning probe based methods. Conductance AFM imaging of the switched bits further reveals correlations between the switched volume, pulse amplitude, and pulse duration. The influence of film heterogeneities on switching is also directly detected, which is of tremendous importance for optimal device performance.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

NASA NTRS1992

A DRAM compiler algorithm for high performance VLSI embedded memories

In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .

Eldin, A. G.↗

DOE OSTI2014

Three-terminal magnetic tunneling junction device with perpendicular anisotropy CoFeB sensing layer

We demonstrated read and write characteristics of a three terminal memory device with a perpendicular anisotropy-free layer of a strip of [Co/Ni] and a low-switching perpendicular-anisotropy CoFeB/MgO sensing layer. This new design of the cell results in a small cell area. The switching magnetic field of the sensing layer can be decreased by changing sputtering gas for the Ta-cap from Ar to Kr. An electron energy-loss spectroscopy analysis of the cross-section of the magnetic tunneling junction (MTJ) revealed that the boron content in CoFeB with a Kr-sputtered Ta-cap was smaller than that with an Ar-sputtered one. A change in resistance for the MTJ was observed that corresponded to the magnetic switching of the Co/Ni wire and its magnetoresistance ratio and critical current were 90% and 0.8 mA, respectively.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2018

Phase field simulation of martensitic transformation in pre-strained nanocomposite shape memory alloys

We show in this paper how strain engineering alters the fundamental characteristic of a martensitic transformation (MT) and gives it a new set of properties including large quasi-linear elastic strain response with nearly vanishing hysteresis and low elastic modulus. The work is motivated and inspired by a recent experimental study on elastic and inelastic (transformation) strain matching in a pre-strained nano-composite with Nb nanowires embedded in a NiTi shape memory alloy matrix. In particular, we demonstrate by computer simulation that dislocations at Nb/NiTi interfaces produced by the pre-straining are responsible for the unprecedented properties. Microstructural evolution captured in the simulations reveals that local stress fields associated with the dislocations regulate the nucleation and growth of martensite, turning the otherwise sharp, strong first-order transition into a continuous, high-order like transition. The simulations predict that the stress-strain hysteresis and modulus of the composite decrease with increasing amount of pre-strain, which agrees well with the experimental measurement. This study suggests a design strategy by introducing non-uniform stress fields for enhanced properties of shape memory alloys.

36 MATERIALS SCIENCE↗

NASA NTRS2024

Cognitive Performance in ISS Astronauts on 6-Month Low Earth Orbit Missions

Introduction: Current and future astronauts will endure prolonged exposure to spaceflight hazards and environmental stressors that could compromise cognitive functioning, yet cognitive performance in current missions to the International Space Station remains critically under-characterized. We systematically assessed cognitive performance across 10 cognitive domains in astronauts on 6-month missions to the ISS. Methods: Twenty-five professional astronauts were administered the Cognition Battery as part of National Aeronautics and Space Administration (NASA) Human Research Program Standard Measures Cross-Cutting Project. Cognitive performance data were collected at five mission phases: pre-flight, early flight, late flight, early post-flight, and late post-flight. We calculated speed and accuracy scores, corrected for practice effects, and derived z-scores to represent deviations in cognitive performance across mission phases from the sample’s mean baseline (i.e., pre-flight) performance. Linear mixed models with random subject intercepts and pairwise comparisons examined the relationships between mission phase and cognitive performance. Results: Cognitive performance was generally stable over time with some differences observed across mission phases for specific subtests. There was slowed performance observed in early flight on tasks of processing speed, visual working memory, and sustained attention. We observed a decrease in risk-taking propensity during late flight and post-flight mission phases. Beyond examining group differences, we inspected scores that represented a significant shift from the sample’s mean baseline score, revealing that 11.8% of all flight and post-flight scores were at or below 1.5 standard deviations below the sample’s baseline mean. Finally, exploratory analyses yielded no clear pattern of associations between cognitive performance and either sleep or ratings of alertness. Conclusions: There was no evidence for a systematic decline in cognitive performance for astronauts on a 6-month missions to the ISS. Some differences were observed for specific subtests at specific mission phases, suggesting that processing speed, visual working memory, sustained attention, and risk-taking propensity may be the cognitive domains most susceptible to change in Low Earth Orbit for high performing, professional astronauts. We provide descriptive statistics of pre-flight cognitive performance from 25 astronauts, the largest published preliminary normative database of its kind to date, to help identify significant performance decrements in future samples.

Data curation↗

DOE OSTI2024

A graphics processing unit accelerated sparse direct solver and preconditioner with block low rank compression

We present the GPU implementation efforts and challenges of the sparse solver package STRUMPACK. The code is made publicly available on github with a permissive BSD license. STRUMPACK implements an approximate multifrontal solver, a sparse LU factorization which makes use of compression methods to accelerate time to solution and reduce memory usage. Multiple compression schemes based on rank-structured and hierarchical matrix approximations are supported, including hierarchically semi-separable, hierarchically off-diagonal butterfly, and block low rank. Here, in this paper, we present the GPU implementation of the block low rank (BLR) compression method within a multifrontal solver. Our GPU implementation relies on highly optimized vendor libraries such as cuBLAS and cuSOLVER for NVIDIA GPUs, rocBLAS and rocSOLVER for AMD GPUs and the Intel oneAPI Math Kernel Library (oneMKL) for Intel GPUs. Additionally, we rely on external open source libraries such as SLATE (Software for Linear Algebra Targeting Exascale), MAGMA (Matrix Algebra on GPU and Multi-core Architectures), and KBLAS (KAUST BLAS). SLATE is used as a GPU-capable ScaLAPACK replacement. From MAGMA we use variable sized batched dense linear algebra operations such as GEMM, TRSM and LU with partial pivoting. KBLAS provides efficient (batched) low rank matrix compression for NVIDIA GPUs using an adaptive randomized sampling scheme. The resulting sparse solver and preconditioner runs on NVIDIA, AMD and Intel GPUs. Interfaces are available from PETSc, Trilinos and MFEM, or the solver can be used directly in user code. We report results for a range of benchmark applications, using the Perlmutter system from NERSC, Frontier from ORNL, and Aurora from ALCF. For a high frequency wave equation on a regular mesh, using 32 Perlmutter compute nodes, the factorization phase of the exact GPU solver is about 6.5× faster compared to the CPU-only solver. The BLR-enabled GPU solver is about 13.8× faster than the CPU exact solver. For a collection of SuiteSparse matrices, the STRUMPACK exact factorization on a single GPU is on average 1.9× faster than NVIDIA’s cuDSS solver.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Stable Metallic Enrichment in Conductive Filaments in TaO x –Based Resistive Switches Arising from Competing Diffusive Fluxes

Oxide–based resistive–switching devices hold promise for solid–state memory technology. Information encoding is accomplished by electrically switching the device between two nonvolatile states with low and high resistance states (LRS/HRS). It is generally accepted that the change between these states is due to the motion of oxygen vacancies forming a continuous (LRS) or gapped (HRS) filament between the electrodes. Direct assessments of filaments are rare due to their small size and the difficulty of locating the filament. Electron microscopy experiments reveal the filament structure and chemistry in TaO 2.0 ± 0.2 –based 150 × 150 nm 2 devices with cross–sectional geometry after forming with power dissipation lower than 1 mW. The filaments appear to be roughly hourglass–shaped with a diameter of less than 10 nm and are composed of Ta–rich and O–poor mostly amorphous material with local compositions as Ta–rich as TaO 0.4 . The as–formed HRS has a gap up to 10 nm wide located next to the anode and composed of nearly stoichiometric TaO 2.5 . The tantalum and oxygen distribution is consistent with filaments formed by the motion of both Ta and O driven by temperature gradients (Soret effect) and an electric field. As a result, this interpretation points towards a new compact model of resistive–switching devices.

36 MATERIALS SCIENCE↗

DOE OSTI2019

Performance Exploration Through Optimistic Static Program Annotations

Compilers are limited by the static information directly or indirectly encoded in the program. Low-level languages, such as C/C++, are considered problematic as their weak type system and relaxed memory semantic allows for various, sometimes non-obvious, behaviors. Since compilers have to preserve the program semantics for all program executions, the existence of exceptional behavior can prevent optimizations that the developer would consider valid and might expect. Analyses to guarantee the absence of disruptive and unlikely situations are consequently an indispensable part of an optimizing compiler. However, such analyses have to be approximative and limited in scope as global and exact solutions are infeasible for any non-trivial program. In this paper, we present an automated tool to measure the effectmissing static information has on the optimizations applied to a given program. The approach generates an optimistically optimized program version which, compared to the original, defines a performance gap that can be closed by better compiler analyses and selective static program annotations. Our evaluation on six already tuned proxy applications for high-performance codes shows speedups of up to 20.6%. This clearly indicates that static uncertainty limits performance. At the same time, we observed that compilers are often unable to utilize additional static information. Thus, manual annotation of all correct static information is therefore not only error prone but also mostly redundant.

Auto Tuning↗

DOE OSTI2015

Electrical characteristics of ZnO nanorods reinforced polymer nanocomposite thin films

ZnO nanorods have been prepared by simple chemical method, which is used to fabricate organic bistable devices (OBDs). OBDs are fabricated by incorporating different weight percent (wt %) of chemically synthesized Zinc Oxide (ZnO) nanorods into polymethylmethacrylate (PMMA). Current-voltage (I-V) measurements of the spin coated ZnO+PMMA nanocomopsite thin film on indium tin oxide (ITO) coated glass substrate showed current hysteresis behaviour, which is an indication of memory effect. The samples exhibit two distinct resistance states, ON and OFF states, characterised by relatively low and high resistance of the OBDs, respectively. It is also observed that with change in ZnO dopant concentration the value of ON/OFF current changes. Higher ON/OFF current ratio is desired for practical applications. Current conduction mechanism of the devices has been explained invoking various existing models, and it has been found that the trapped-charge-limited conduction mechanism was dominant in our samples.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2019

Quasi-one-dimensional ferroelectricity and piezoelectricity in WOX 4 halogens

A series of oxytetrahalides WOX 4 (X: a halogen element) that form quasi-one-dimensional chains is investigated using first-principles calculations. The crystal structures, electronic structures, as well as ferroelectric and piezoelectric properties are discussed in detail. Group theory analysis shows that the ferroelectricity in this family originates from an unstable polar phonon mode Γ$_1^-$ induced by the W's d0 orbital configuration. Their polarization magnitudes are found to be comparable to widely used ferroelectric perovskites. Because of its quasi-one-dimensional characteristics, the interchain domain wall energy density is low, leading to loosely coupled ferroelectric chains. This is potentially beneficial for high-density ferroelectric memories: We estimate that the upper limit of memory density in these compounds could reach hundreds of terabytes per square inch.

1-dimensional systems↗

DOE OSTI2025

If We Build Them, They Will Run: Automated HPC Apps Deployment and Profiling with eBPF in Cloud

The high performance computing (HPC) community is in a period of transition. The rise of AI/ML coupled with a changing landscape of resources deems portability a new metric of performance, and methods to move between on-premises and cloud environments and assess compatibility are paramount. Here we design and test a strategy for bridging the gap between traditional HPC and Kubernetes environments – first containerizing applications, providing automated orchestration to run studies, and packaging the setup with automated means to assess performance using low overhead eXtended Berkeley Packet Filter (eBPF) programs. We first assess different designs for eBPF collection, demonstrating a tradeoff between number of programs deployed on a node and overhead added. We develop 5 low overhead eBPF programs that combine with streaming ML models to assess CPU, futex, TCP, shared memory, and file access across four different builds of an HPC application for CPU and GPU. We use eBPF data to generate insights into the possible underlying etiology of scaling issues. We then assess compatibility of a well-known benchmark, HPCG, across matrices of micro-architectures and optimization levels (217 containers across 24 instance types and over 7500 runs). We provide to the community 30 applications to deploy in our automated setup and perform a scaling study from 4 to a maximum of 256 nodes for both CPU and GPU applications. Finally, we use our gained knowledge about performance to generate compatibility artifacts that are used by a newly developed Kubernetes controller to intelligently select instance type based on optimizing a figure of merit. Along with insights to scaling in this environment with a collection of applications and templates to work from, we provide an overall strategy for approaching HPC application deployment and image selection based on compatibility in cloud.

Computer science↗