Results for “logic” — Page 33

NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗

NASA NTRS2009

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

DeGregorio, Kelly↗

NASA NTRS2010

Efficient Web Services Policy Combination

Large-scale Web security systems usually involve cooperation between domains with non-identical policies. The network management and Web communication software used by the different organizations presents a stumbling block. Many of the tools used by the various divisions do not have the ability to communicate network management data with each other. At best, this means that manual human intervention into the communication protocols used at various network routers and endpoints is required. Developing practical, sound, and automated ways to compose policies to bridge these differences is a long-standing problem. One of the key subtleties is the need to deal with inconsistencies and defaults where one organization proposes a rule on a particular feature, and another has a different rule or expresses no rule. A general approach is to assign priorities to rules and observe the rules with the highest priorities when there are conflicts. The present methods have inherent inefficiency, which heavily restrict their practical applications. A new, efficient algorithm combines policies utilized for Web services. The method is based on an algorithm that allows an automatic and scalable composition of security policies between multiple organizations. It is based on defeasible policy composition, a promising approach for finding conflicts and resolving priorities between rules. In the general case, policy negotiation is an intractable problem. A promising method, suggested in the literature, is when policies are represented in defeasible logic, and composition is based on rules for non-monotonic inference. In this system, policy writers construct metapolicies describing both the policy that they wish to enforce and annotations describing their composition preferences. These annotations can indicate whether certain policy assertions are required by the policy writer or, if not, under what circumstances the policy writer is willing to compromise and allow other assertions to take precedence. Meta-policies are specified in defeasible logic, a computationally efficient non-monotonic logic developed to model human reasoning. One drawback of this method is that at one point the algorithm starts an exhaustive search of all subsets of the set of conclusions of a defeasible theory. Although the propositional defeasible logic has linear complexity, the set of conclusions here may be large, especially in real-life practical cases. This phenomenon leads to an inefficient exponential explosion of complexity. The current process of getting a Web security policy from combination of two meta-policies consists of two steps. The first is generating a new meta-policy that is a composition of the input meta-policies, and the second is mapping the meta-policy onto a security policy. The new algorithm avoids the exhaustive search in the current algorithm, and provides a security policy that matches all requirements of the involved metapolicies.

Vatan, Farrokh↗

NASA NTRS2009

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Neudeck, Philip G.↗

NASA NTRS2004

Ultralow-Power Digital Correlator for Microwave Polarimetry

A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the autocorrelations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two intermediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2(exp 8) cycles of the sampling clock, up to a maximum of 2(exp 24) cycles. The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2(exp 8) the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over.

Piepmeier, Jeffrey R.↗

NASA NTRS2013

High-Speed, High-Resolution Time-to-Digital Conversion

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

Katz, Richard↗

NASA NTRS2014

Weather Forecasting Systems and Methods

A weather forecasting system has weather forecasting logic that receives raw image data from a satellite. The raw image data has values indicative of light and radiance data from the Earth as measured by the satellite, and the weather forecasting logic processes such data to identify cumulus clouds within the satellite images. For each identified cumulus cloud, the weather forecasting logic applies interest field tests to determine a score indicating the likelihood of the cumulus cloud forming precipitation and/or lightning in the future within a certain time period. Based on such scores, the weather forecasting logic predicts in which geographic regions the identified cumulus clouds will produce precipitation and/or lighting within during the time period. Such predictions may then be used to provide a weather map thereby providing users with a graphical illustration of the areas predicted to be affected by precipitation within the time period.

Mecikalski, John↗

NASA NTRS2017

Simulink(Trademark) Controller for a Reluctance Motor With a Four-Pole Rotor and 36-Tooth Stator

NASA Glenn Research Center has developed a Simulink(Trademark) controller logic for driving a room temperature, 36-teeth stator, four-pole rotor reluctance motor. The Simulink logic was extracted from an existing C++ motor controller that was previously employed to achieve a rotor speed of 3000 rpm. The Simulink controller has additional logic refinements that were not available in past C++ controller, such as the per rev logic component and its frequency filter. The filter provides a more accurate reading of the rotor input signals. The controller is versatile, and with slight modifications, can be used to drive other reluctance motor types incorporating dissimilar stator rotor pole combinations. The original C++ controller was designed with the goal (after appropriate modification) of controlling a future superconducting motor. This superconducting motor will be employed as a test bed for developing other superconducting aviation propulsion motors envisioned for future turbo-electric aircrafts. The Simulink results presented in this paper were generated from simulated rotor inputs. However, in an actual application, these simulated inputs are to be replaced by actual proximity probe signals emanating from D-Space hardware inputs.

Motor Controller↗

NASA NTRSDate not supplied

Controls Algorithms, Models, and Stability Assessments of the RCS and TVC systems on Mars Ascent Vehicle

This paper presents a control systems overview of the Mars Ascent Vehicle (MAV) control design and stability analysis with two separate control methods: Thrust Vector Control (TVC) based control using main engine thrust and Reaction Control System (RCS) via thrusters. A pole-placement TVC controller is proposed to address quickly peaking thrust produced by the MAV solid propulsion engine. The controllerutilizes real-time parameter estimation to calculate control gains using an online pole-placement method. The pole-placement technique allows the controller to maintain constant stability margins throughout the flight under changing parameters and rapidly peaking thrust. A mathematical stability proof via Lyapunov inequality and Nichols method is demonstrated to support the stability of the method. In addition to the TVC control, a phase-plane based RCS control logic is applied to the vehicle for roll control during ascent and all axes during coast phases of flight. The logic implemented is an on-off type logic that applies pre-determined thrusters firings in reference to boundary parameters of pointing and rate error chosen to balance desired pointing with stability. A describing function methodology is applied to the non-linear phase plane loop response to determine linear stability across all flight phases. The controller additionally applies command alteration logic to output signals to account for RCS hardware limitations. The following paper will provide the methodology for controller implementation of the TVC and RCS, and provide a summary of results of the MAV performance applying the aforementioned control design.

Han Woong Bae↗

NASA NTRS2018

The DejaVu Runtime Verification Benchmark

In this paper we present a benchmark for evaluating runtime veriﬁcation tools. It was originally created in order to compare the DEJAVU runtime veriﬁcation tool1 with another similar tool. DEJAVU’s logic is ﬁrst-order past time temporal logic. In order to monitor such properties efﬁciently, Binary Decision Diagrams (BDDs) [1] are used for representing the data observed in a trace. The details on the logic and its algorithm are described in e.g. [2, 3, 4]. The benchmark consists of six properties, formulated in English, and formalized in DEJAVU’s logic. For each property is provided (normally) three traces, of sizes varying from 10,000 events to one million events. Traces are represented in CSV format.

Ulus, Dogan↗

NASA NTRSDate not supplied

Formal Methods in the Development of Highly Assured Software for Unmanned Aircraft Systems

In traditional software development methodologies, operational and functional requirements of systems are often specified in structured natural language notations. These restricted notations provide good documentation support, but only provide limited support for semantic analysis. These notations are generally not rich enough to unambiguously specify the requirements of safety-critical systems that, for example, involve complex numerical computations or that interact with the physical environment. Examples of these safety-critical systems are autonomous vehicles such as unmanned aircraft systems. This talk advocates the use of expressive formal logics, such as higher-order logic, to specify the operational and functional requirement of unmanned systems and to prove the correctness of these requirements. Semantic analysis of requirements written in higher-order logic is supported through the use of interactive theorem provers. Formal models serve as ideal reference implementations of functional requirements. Hence, formal logics enable software validation techniques where software implementations can be checked against functional requirements in a mechanical way. The Formal Methods group in the Safety-Critical Avionics Systems Branch at NASA Langley Research Center has conducted research on the development and application of formal verification techniques to safety-critical applications of interest to NASA for more than 30 years. This talk illustrates the use of formal methods in the development of highly-assured autonomous unmanned aircraft systems.

Formal Methods↗

NASA NTRS2023

Transient Optimization for the Betterment of Turbine Electrified Energy Management

Gas turbine engine transients are associated with degraded compressor operability, which must be addressed by the engine control system and accounted for in the engine design. Failure to do so may result in events such as compressor stall/surge and combustor blow out. Transient operability concerns constrain the engine design and can result in sacrifices of efficiency and/or thrust responsiveness. The traditional approach to transient operability management is control logic that limits the fuel flow command. A companion paper presents a strategy for optimizing the transient fuel flow control logic taking into consideration transient operability and thrust responsiveness. The study covered here extends this idea to an electrified gas turbine engine that employs a power/energy management concept known as Turbine Electrified Energy Management (TEEM). TEEM uses an electric power system interfaced with the engine (hence the term ‘electrified gas turbine engine’) to further improve transient operability and alleviate associated design constraints. There can be costs associated with implementing TEEM in terms of power and energy requirements that impact the size of the electrical power system. However, the results of this study show that through optimization of the transient limit logic, power and energy requirements needed to implement TEEM can be significantly reduced. Among the conclusions that can be drawn from the results of the illustrative application covered herein are: (1) there is a reduction in the electric machine power requirement to manage operability during accelerations by 200 to 400 hp, and (2) power transfer from the low pressure spool (LPS) to the high pressure spool (HPS) is the most effective option for improving operability during decelerations, followed by the options of only injecting power on the HPS or only extracting power from the LPS.

Turbine Electrified Energy Management↗

NASA NTRSDate not supplied

Transient Optimization for the Betterment of Turbine Electrified Energy Management

Gas turbine engine transients are associated with degraded compressor operability, which must be addressed by the engine control system and accounted for in the engine design. Failure to do so may result in events such as compressor stall/surge and combustor blow out. Transient operability concerns constrain the engine design and can result in sacrifices of efficiency and/or thrust responsiveness. The traditional approach to transient operability management is control logic that limits the fuel flow command. A companion paper presents a strategy for optimizing the transient fuel flow control logic taking into consideration transient operability and thrust responsiveness. The study covered here extends this idea to an electrified gas turbine engine that employs a power/energy management concept known as Turbine Electrified Energy Management (TEEM). TEEM uses an electric power system interfaced with the engine (hence the term ‘electrified gas turbine engine’) to further improve transient operability and alleviate associated design constraints. There can be costs associated with implementing TEEM in terms of power and energy requirements that impact the size of the electrical power system. However, the results of this study show that through optimization of the transient limit logic, power and energy requirements needed to implement TEEM can be significantly reduced. Among the conclusions that can be drawn from the results of the illustrative application covered herein are: (1) there is a reduction in the electric machine power requirement to manage operability during accelerations by 200 to 400 hp, and (2) power transfer from the low pressure spool (LPS) to the high pressure spool (HPS) is the most effective option for improving operability during decelerations, followed by the options of only injecting power on the HPS or only extracting power from the LPS.

transient↗

NASA NTRSDate not supplied

Transient Optimization for the Betterment of Turbine Electrified Energy Management

Gas turbine engine transients are associated with degraded compressor operability, which must be addressed by the engine control system and accounted for in the engine design. Failure to do so may result in events such as compressor stall/surge and combustor blow out. Transient operability concerns constrain the engine design and can result in sacrifices of efficiency and/or thrust responsiveness. The traditional approach to transient operability management is control logic that limits the fuel flow command. A companion paper presents a strategy for optimizing the transient fuel flow control logic taking into consideration transient operability and thrust responsiveness. The study covered here extends this idea to an electrified gas turbine engine that employs a power/energy management concept known as Turbine Electrified Energy Management (TEEM). TEEM uses an electric power system interfaced with the engine (hence the term ‘electrified gas turbine engine’) to further improve transient operability and alleviate associated design constraints. There can be costs associated with implementing TEEM in terms of power and energy requirements that impact the size of the electrical power system. However, the results of this study show that through optimization of the transient limit logic, power and energy requirements needed to implement TEEM can be significantly reduced. Among the conclusions that can be drawn from the results of the illustrative application covered herein are: (1) there is a reduction in the electric machine power requirement to manage operability during accelerations by 200 to 400 hp, and (2) power transfer from the low pressure spool (LPS) to the high pressure spool (HPS) is the most effective option for improving operability during decelerations, followed by the options of only injecting power on the HPS or only extracting power from the LPS.

transient↗

NASA NTRS1970

Ground computer test trap

Test trap consists of logic nest of five printed circuit boards, plus power supply within the unit. Device monitors more than one logic area simultaneously, gives visual display of detected error, operates at computer speed, maintains readily available logic description of cards used, and is compatible with existing computer circuitry.

Fondrie, D. G.↗

NASA NTRS1971

Simulation of Mariner Mars 1971 spacecraft

Preparation for the Mariner Mars 1971 mission is reported, including an extensive training program for operations personnel during which the primary source of spacecraft data was a computer program simulating the spacecraft. The objectives of a simulation model for training purposes differed from objectives appropriate to a design or analysis model. Model subsystems were designed to provide realistic telemetry data reflecting changes due both to commands and environmental parameters affecting the spacecraft at various times during the mission. The spacecraft is modeled along two separate functional lines. Boolean operations are concentrated in the spacecraft logic model, which determines the spacecraft state or mode, while mathematical operations or algorithms are executed in computational subsystem models. Although logic parameters are interrogated as a part of each computational pass, actual logic model processing occurs only when a change-of-state input is generated by the operations organization. The program design, some of the special characteristics of each of the modeled subsystems, and how the model was used in support of mission operations training are presented.

Ausman, N. E., Jr.↗

NASA NTRS1971

Design, development, fabrication and delivery of register and multiplexer units

Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.

Feller, A.↗

NASA NTRS1972

Design of automata theory of cubical complexes with applications to diagnosis and algorithmic description

The following problems are considered: (1) methods for development of logic design together with algorithms, so that it is possible to compute a test for any failure in the logic design, if such a test exists, and developing algorithms and heuristics for the purpose of minimizing the computation for tests; and (2) a method of design of logic for ultra LSI (large scale integration). It was discovered that the so-called quantum calculus can be extended to render it possible: (1) to describe the functional behavior of a mechanism component by component, and (2) to compute tests for failures, in the mechanism, using the diagnosis algorithm. The development of an algorithm for the multioutput two-level minimization problem is presented and the program MIN 360 was written for this algorithm. The program has options of mode (exact minimum or various approximations), cost function, cost bound, etc., providing flexibility.

Roth, J. P.↗