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At least 595 records · Page 33
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Nanophotonic waveguide chip-to-world beam scanning

A seamless chip-to-world photonic interface enables broad advancements in optical ranging, display, communication, computation and quantum information science. The ideal solution enables two-dimensional scanning of a diffraction-limited beam from anywhere on a photonic integrated circuit to a large number of resolvable spots. Current beam-scanning technologies are limited by a fundamental trade-off: photonic-integrated-circuits with diffractive optics offer scalability but have poor mode quality, whereas inertially limited micromechanical scanners provide high-quality beams but lack scalable integration. Here we report a photonic ski-jump—a nanoscale waveguide monolithically integrated on a piezoelectric cantilever—to overcome these limitations. It passively curls ~90° out-of-plane within a less-than-0.1 mm 2 footprint, emits a submicrometre, broadband diffraction-limited beam, and exhibits kilohertz-rate mechanical resonances with quality factors of over 10,000. Fabricated in a volume complementary metal–oxide–semiconductor (CMOS) foundry, our device enables scalable two-dimensional beam scanning. Driven on-resonance at CMOS-level voltages, it achieves a footprint-adjusted spot rate of 68.6 mega spots s –1 mm–², exceeding state-of-the-art micro-electro-mechanical systems mirrors by more than 50-fold, which is sufficient for one million pixels at 100 Hz from an approximately 1.5 mm diameter footprint. We demonstrate full-colour image and video projection, and single-photon initialization and readout from silicon vacancy centres in diamond. Finally, by demonstrating uniformity across a 64 ski-jump array, we establish a pathway to achieving greater than one gigaspot resolution at kilohertz rates within a sub-5-cm-diameter footprint, creating a seamless optical pipeline between integrated photonic processors and the free-space world.

Displays↗
NASA NTRS1999

Innovative, Inexpensive Etching Technique Developed for Polymer Electro- Optical Structures

Electro-optic, polymer-based integrated optic devices for high-speed communication and computing applications offer potentially significant advantages over conventional inorganic electro-optic crystals. One key area of integrated optical technology--primary processing and fabrication--may particularly benefit from the use of polymer materials. However, as efforts concentrate on the miniaturization of electro-integrated circuit pattern geometries, the ability to etch fine features and smoothly sloped sidewalls is essential to make polymers useful for electro-integrated circuit applications. There are many existing processes available to etch polymer materials, but they all yield nearly vertical sidewalls. Vertical sidewalls are too difficult to reliably cover with a metal layer, and incomplete metalization degrades microwave performance, particularly at high frequency. However, obtaining a very sloped sidewall greatly improves the deposition of metal on the sidewall, leading to low-loss characteristics, which are essential to integrating these devices in highspeed electro-optic modulators. The NASA Lewis Research Center has developed in-house an inexpensive etching technique that uses a photolithography method followed by a simple, wet chemical etching process to etch through polymer layers. In addition to being simpler and inexpensive, this process can be used to fabricate smoothly sloped sidewalls by using a commercial none rodible mask: Spin-On-Glass. A commercial transparent material, Spin-On-Glass, uses processes and equipment similar to that for photoresist techniques.

Nguyen, Hung D.↗
DOE OSTI2022

Low voltage AC electroluminescence in silicon MOS capacitors

Low power silicon based light source and detector are attractive for on-chip photonic circuits given their ease of process integration. However, conventional silicon light emitting diodes emit photons with energies near the band edge where the corresponding silicon photodetectors lack responsivity. On the other hand, previously reported hot carrier electroluminescent silicon devices utilizing a reverse biased diode require high operating voltages. Here, we investigate hot carrier electroluminescence in silicon metal–oxide–semiconductor capacitors operating under transient voltage conditions. Further, during each voltage transient, large energy band bending is created at the edge of the source contact, much larger than what is achievable at a steady state. As a result, electrons and holes are injected efficiently from a single source contact into the silicon channel at the corresponding voltage transient, where they subsequently undergo impact ionization and phonon-assisted interband recombination. Notably, we show low voltage operation down to 2.8 V by using a 20 nm thick high-κ gate dielectric. We show further voltage scaling is possible by reducing the gate dielectric thickness, thus presenting a low voltage platform for silicon optoelectronic integrated circuits.

42 ENGINEERING↗
NASA NTRS1988

System Measures Logic-Gate Delays

Many gates on chip tested automatically. Automatic testing system measures signal-propagation delays of experimental integrated-circuit array of logic gates. Includes controlling computer, counter/time, and feedback-controlled timing-waveform generator. Multiplexer included on integrated-circuit chip with logic-gate array to be tested. Delays measured by system serve as valuable data for design of fast logic and memory chips.

Blaes, Brent R.↗
NASA NTRS2007

Assessment of SOI Devices and Circuits at Extreme Temperatures

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Elbuluk, Malik↗
NASA NTRS2010

Ka-Band Waveguide Two-Way Hybrid Combiner for MMIC Amplifiers

The design, simulation, and characterization of a novel Ka-band (32.05 0.25 GHz) rectangular waveguide two-way branch-line hybrid unequal power combiner (with port impedances matched to that of a standard WR-28 waveguide) has been created to combine input signals, which are in phase and with an amplitude ratio of two. The measured return loss and isolation of the branch-line hybrid are better than 22 and 27 dB, respectively. The measured combining efficiency is 92.9 percent at the center frequency of 32.05 GHz. This circuit is efficacious in combining the unequal output power from two Ka-band GaAs pseudomorphic high electron mobility transistor (pHEMT) monolithic microwave integrated circuit (MMIC) power amplifiers (PAs) with high efficiency. The component parts include the branch-line hybrid-based power combiner and the MMIC-based PAs. A two-way branch-line hybrid is a four-port device with all ports matched; power entering port 1 is divided in phase, and into the ratio 2:1 between ports 3 and 4. No power is coupled to port 2. MMICs are a type of integrated circuit fabricated on GaAs that operates at microwave frequencies, and performs the function of signal amplification. The power combiner is designed to operate over the frequency band of 31.8 to 32.3 GHz, which is NASA's deep space frequency band. The power combiner would have an output return loss better than 20 dB. Isolation between the output port and the isolated port is greater than 25 dB. Isolation between the two input ports is greater than 25 dB. The combining efficiency would be greater than 90 percent when the ratio of the two input power levels is two. The power combiner is machined from aluminum with E-plane split-block arrangement, and has excellent reliability. The flexibility of this design allows the combiner to be customized for combining the power from MMIC PAs with an arbitrary power output ratio. In addition, it allows combining a low-power GaAs MMIC with a high-power GaN MMIC. The arbitrary port impedance allows matching the output impedance of the MMIC PA directly to the waveguide impedance without transitioning first into a transmission line with characteristic impedance of 50 ohms. Thus, by eliminating the losses associated with a transition, the overall SSPA efficiency is enhanced. For reducing the cost and weight when required in very large quantities, such as in the beam-forming networks of phased-array antenna systems, the combiner can be manufactured using metal-plated plastic. Two hybrid unequal power combiners can be cascaded to realize a non-binary combiner (for e.g., a three-way) and can be synergistically optimized for low VSWR (voltage standing wave ratio), low insertion loss, high isolation, and wide bandwidth using commercial off-the-shelf electromagnetic software design tools.

Simons, Rainee N.↗
DOE OSTI2024

Radio Frequency Properties of a 3D Printed Klystron Circuit

The manufacturing of active RF devices like klystrons is dominated by expensive and time-consuming cycles of machining and brazing. In this article, we characterize the RF properties of X-band klystron cavities and an integrated circuit manufactured with a novel additive manufacturing process. Parts are 3D printed in 316 L stainless steel with direct metal laser sintering, electroplated in copper, and brazed in one simple braze cycle. Stand-alone test cavities and integrated circuit cavities were measured throughout the manufacturing process. The un-tuned cavity frequency varies by less than 5% of the intended frequency, and Q factors reach above 1200. A tuning study was performed, and unoptimized tuning pins achieved a tuning range of 138 MHz without compromising Q. Klystron system performance was simulated with as-built cavity parameters and realistic tuning. Together, these results show promise that this process can be used to cheaply and quickly manufacture a new generation of highly integrated high power vacuum devices.

3D printing↗
NASA NTRS1977

Changing NRZ data to biphase logic

Simple arrangement of four integrated circuits changes stream of binary data from non-return-to-zero (NRZ) coding to biphase logic coding. Selection of wiring and integrated circuits enables control and balancing of propagation delay without requiring excessive and expensive hardware.

Baker, E. B.↗
NASA NTRS1987

Parallel Analog-to-Digital Image Processor

Proposed integrated-circuit network of many identical units convert analog outputs of imaging arrays of x-ray or infrared detectors to digital outputs. Converter located near imaging detectors, within cryogenic detector package. Because converter output digital, lends itself well to multiplexing and to postprocessing for correction of gain and offset errors peculiar to each picture element and its sampling and conversion circuits. Analog-to-digital image processor is massively parallel system for processing data from array of photodetectors. System built as compact integrated circuit located near local plane. Buffer amplifier for each picture element has different offset.

Lokerson, D. C.↗
NASA NTRS1993

Energetic Atoms Would Etch Photoresists Anisotropically

Directed beams of single oxygen atoms having kinetic energies between 1 and 5 eV used in anisotropic etching of oxygen-labile photoresist patterns on silicon wafers. Key step in manufacturing integrated circuits on semiconductor wafers. Damage to semiconductor material under photoresist layer reduced or eliminated. Method incorporated into lithographic processes for fabrication of integrated circuits.

Koontz, Steven↗
NASA NTRS2010

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Patterson, Richard↗
DOE OSTI2022

Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications

Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
NASA NTRS2009

Biasable Subharmonic Membrane Mixer for 520 to 600 GHz

The figure shows a biasable subharmonic mixer designed to operate in the frequency range from 520 to 600 GHz. This mixer is a prototype of low-power mixers needed for development of wideband, high-resolution spectrometers for measuring spectra of molecules in the atmospheres of Earth, other planets, and comets in the frequency range of 400 to 700 GHz. Three considerations dictated the main features of the design: It is highly desirable to operate the spectrometers at or slightly below room temperature. This consideration is addressed by choosing Schottky diodes as the frequency-mixing circuit elements because of all mixer diodes, Schottky diodes are the best candidates for affording sufficient sensitivity at or slightly below room-temperature range. The short wavelengths in the intended operating-frequency range translate to stringent requirements for precision of fabrication and assembly of the circuits; these requirements are even more stringent for wide-bandwidth circuits. This consideration is addressed in two ways: (1) As much as possible of the mixer circuitry is fabricated in the form of a monolithic integrated circuit on a GaAs membrane, employing a modified version of a process used previously to fabricate a non-subharmonic mixer for a frequency of 2.5 THz and frequency multipliers for frequencies up to 2 THz. (2) The remainder of the circuitry is precision machined into a waveguide block that holds the GaAs integrated circuit.

Schlecht, Erich↗
NASA NTRS2007

IC and Component Selection for Space Systems

This viewgraph presentation reviews the integrated circuit (IC) and selections of the IC components for space systems. Included in the discussion are a overview of semiconductors and the evolution of integrated circuit. It also reviews the three different viewpoints of the IC selection: technical, programmatic, and risk. From a radiation perspective there are four criteria for selecting ICs for space systems: guaranteed hardness, historical ground-based data, historical flight usage, and unknown assurance.

Label, Kenneth A.↗
NASA NTRS2011

High Frequency PIN-Diode Switches for Radiometer Applications

Internally calibrated radiometers are needed for ocean topography and other missions. Typically internal calibration is achieved with Dicke switching as one of the techniques. We have developed high frequency single-pole double-throw (SPDT) switches in the form of monolithic microwave integrated circuits (MMIC) that can be easily integrated into Dicke switched radiometers that utilize microstrip technology. In particular, the switches we developed can be used for a radiometer such as the one proposed for the Surface Water and Ocean Topography (SWOT) Satellite Mission whose three channels at 92, 130, and 166 GHz would allow for wet-tropospheric path delay correction near coastal zones and over land. This feat is not possible with the current Jason-class radiometers due to their lower frequency signal measurement and thus lower resolution. The MMIC chips were fabricated at NGST using their InP PIN diode process and measured at JPL using high frequency test equipment. Measurement and simulation results will be presented.

PIN-diode↗
DOE OSTI2025

One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics

Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.

2D electronics↗
NASA NTRS1994

Monolithic Optical-To-Electronic Receiver

Monolithic optoelectronic integrated circuit converts multiplexed digital optical signals into electrical signals, separates, and distributes them to intended destinations. Developed to deliver phase and amplitude commands to monolithic microwave integrated circuits (MMIC's) at elements of millimeter-wave phased-array antenna from single optical fiber driven by external array controller. Also used in distribution of high-data-rate optical communications in local-area networks (LAN's). Notable features include options for optical or electrical clock inputs; outputs for raw data, addresses, and instructions for diagnosis; and optical-signal-detection circuit used to reduce power consumption by 80 percent between data-transmission times. Chip fabricated by processes available at many major semiconductor foundries. Distribution of digital signals in aircraft, automobiles, and ships potential application.

Kunath, Richard↗
NASA NTRS1974

Rotating raster generator

A rotating raster generator is provided which enables display of a television raster at any arbitrary roll angle. The generator includes four integrator circuits each of which receives a first voltage input corresponding to the sine or cosine of the desired roll angle and a second input comprising conventional horizontal or vertical sync pulses. The integrator circuits each comprise an operational amplifier and a capacitor connected for producing a ramp output having a rate of change proportional to the roll angle input, an electronic switch responsive to the sync input for resetting the integrator, and a summer that adds the ramp output of the integrator to the roll angle input so as to provide a zero-centered deflection control voltage.

Wagner, C. A.↗