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At least 595 records · Page 33

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NASA NTRS1976

Aspects of job scheduling

A mathematical model for job scheduling in a specified context is presented. The model uses both linear programming and combinatorial methods. While designed with a view toward optimization of scheduling of facility and plant operations at the Deep Space Communications Complex, the context is sufficiently general to be widely applicable. The general scheduling problem including options for scheduling objectives is discussed and fundamental parameters identified. Mathematical algorithms for partitioning problems germane to scheduling are presented.

Phillips, K.↗

NASA NTRS1977

Sin(x)2 + cos(x)2 = 1

Attempts to achieve tasteful automatic employment of the identities sin sq x + cos sq x = 1 and cos sq h x -sin sq h x = 1 in a manner which truly minimizes the complexity of the resulting expression are described. The disappointments of trigonometric reduction, trigonometric expansion, pattern matching, Poisson series, and Demoivre's theorem are related. The advantages of using the method of comparative combinatorial substitutions are illustrated.

Stoutemyer, D. R.↗

NASA NTRS1976

Behavior of queues at signalized intersections in heavy traffic

This paper derives the asymptotic behavior of traffic queues at signalized intersections when the excess of departure capacity over arrivals approaches zero from above. The most interesting result is that the distribution of queue length approaches a negative exponential, with fewer restrictive assumptions than hitherto known. The main improvement results from more precise use of a combinatorial lemma of Spitzer, giving the maximum of the partial sums of a sequence of independent identically distributed random variables, plus some specific constructive probability calculations, many of them involving the Fourier transform. New results are presented on the probability that the queue be below a fixed bound and/or on the probability that the queue be empty. Applications to on-line estimators for real-time traffic control are suggested.

Posner, E. C.↗

NASA NTRS1977

On the existence of binary simplex codes

Using a simple combinatorial construction, the existence of a binary simplex code with m codewords for all m is greater than or equal to 1 is proved. The problem of the shortest possible length is left open.

Taylor, H.↗

NASA NTRS1978

The Lovasz bound and some generalizations

The zero error capacity of a discrete memoryless channel is defined as the largest rate at which information can be transmitted over the channel with zero error probability. One channel with five inputs and outputs whose zero capacity remained unsolved until very recently is considered. An extremely powerful and general technique phased in terms of graph theory, for studying combinatorial packing problems is presented. In particular, Delsarte's linear programming bound for cliques in association schemes appears as a special case of the Lovasz bound.

Mceliece, R. J.↗

NASA NTRS1978

An upper bound for codes in a two-access binary erasure channel

A method for determining an upper bound for the size of a code for a two-access binary erasure channel is presented. For uniquely decodable codes, this bound gives a combinatorial proof of a result by Liao. Examples of the bound are given for codes with minimum distance 4.

Van Tilborg, H. C. A.↗

NASA NTRS1979

Efficient feature subset selection with probabilistic distance criteria

Recursive expressions are derived for efficiently computing the commonly used probabilistic distance measures as a change in the criteria both when a feature is added to and when a feature is deleted from the current feature subset. A combinatorial algorithm for generating all possible r feature combinations from a given set of s features in (s/r) steps with a change of a single feature at each step is presented. These expressions can also be used for both forward and backward sequential feature selection.

Chittineni, C. B.↗

NASA NTRS1978

FTMP - A highly reliable Fault-Tolerant Multiprocessor for aircraft

The FTMP (Fault-Tolerant Multiprocessor) is a complex multiprocessor computer that employs a form of redundancy related to systems considered by Mathur (1971), in which each major module can substitute for any other module of the same type. Despite the conceptual simplicity of the redundancy form, the implementation has many intricacies owing partly to the low target failure rate, and partly to the difficulty of eliminating single-fault vulnerability. An extensive analysis of the computer through the use of such modeling techniques as Markov processes and combinatorial mathematics shows that for random hard faults the computer can meet its requirements. It is also shown that the maintenance scheduled at intervals of 200 hr or more can be adequate most of the time.

Hopkins, A. L., Jr.↗

NASA NTRS1980

LSI logic for phase-control rectifiers

Signals for controlling phase-controlled rectifier circuit are generated by combinatorial logic than can be implemented in large-scale integration (LSI). LSI circuit saves space, weight, and assembly time compared to previous controls that employ one-shot multivibrators, latches, and capacitors. LSI logic functions by sensing three phases of ac power source and by comparing actual currents with intended currents.

Dolland, C.↗

NASA NTRS1980

MIL-M-38510/470 test vectors: Fault detection efficiency measurement via hardware fault simulation

The stuck fault detection efficiency of the test vectors developed for the MIL-M-38510/470 NASA was measured using a hardware stuck fault simulator for the 1802 microprocessor. Thirty-nine stuck faults were not detected out of a total of 874 injected into the combinatorial and sequential parts of the microprocessor. Since undetected faults can create catastrophic errors in equipment designed for high reliability applications, it is recommended that the MIL-M-38510/470 NASA be enhanced with additional test vectors so as to achieve 100% stuck fault detection efficiency.

Timoc, C. C.↗

NASA NTRS1981

Reliability analysis of the F-8 digital fly-by-wire system

The F-8 Digital Fly-by-Wire (DFBW) flight test program intended to provide the technology for advanced control systems, giving aircraft enhanced performance and operational capability is addressed. A detailed analysis of the experimental system was performed to estimated the probabilities of two significant safety critical events: (1) loss of primary flight control function, causing reversion to the analog bypass system; and (2) loss of the aircraft due to failure of the electronic flight control system. The analysis covers appraisal of risks due to random equipment failure, generic faults in design of the system or its software, and induced failure due to external events. A unique diagrammatic technique was developed which details the combinatorial reliability equations for the entire system, promotes understanding of system failure characteristics, and identifies the most likely failure modes. The technique provides a systematic method of applying basic probability equations and is augmented by a computer program written in a modular fashion that duplicates the structure of these equations.

Brock, L. D.↗

NASA NTRS1980

Test vectors development and optimization for a microprocessor

This paper describes a method for generating and optimizing test vectors for a microprocessor, with the aid of a fault simulator implemented entirely by hardware. The development and optimization of test vectors has been done on a tester, with the fault simulator plugged directly into the test head. The fault simulator is capable of automatically injecting over a thousand single or multiple stuck faults in the sequential and combinatorial parts of the microprocessor. The test vectors developed by a programmer working interactively with the tester were applied through the tester to the fault simulator, and the percent of faults detected was measured. The vectors were developed and optimized for the 1802 microprocessor, with the objective of detecting 100% of the single stuck faults with a minimum set of vectors. Experimental results show that 99.7% of the single stuck faults are being detected with approximately 14,000 vectors.

Timoc, C. C.↗

NASA NTRS1982

NASA payload interface verification requirements - Process and implementation

The separate and combinatorial roles played by NASA and STS payload contractors in the processes of interfacing cargo with the Shuttle are described. NASA personnel aid payload interface verification beginning at the hardware development level and perform independent interface verification once the payload is delivered to the payload processing facility. The cargo is first checked for operational and flight readiness, including inspection of installed devices to specification for the interface connections. Checklists furnished to the user are returned to NASA prior to integration simulation unless formal statements of compliance or waivers are exchanged. The continuance of strict adherence to predelivery interface verification testing is emphasized as necessary for meeting the turnaround times projected for the Orbiter fleet.

Huffstetler, W. J.↗

NASA NTRS1983

Logic Simulator Program

The source code for the SPICE 2 program was deblocked in order to isolate and compile the subroutine in an effort to provide a software simulation of discrete and combinatorial electronic components. Incompatibilities between the UNIVAC 1180 FORTRAN and the Sigma V CP-V FORTRAN 4 were resolved. The SPICE 2 model is to be used to determine gate and fan-out delays, logic state conditions, and signal race conditions for transistor array elements and circuit logic to be patterned in the (SPI) 7101 CMOS silicon gate semicustom array. The simulator is to be operable from the CP-V time sharing terminals.

Agarwal, R. K.↗

NASA NTRS1984

A high-speed digital signal processor for atmospheric radar, part 7.3A

The Model SP-320 device is a monolithic realization of a complex general purpose signal processor, incorporating such features as a 32-bit ALU, a 16-bit x 16-bit combinatorial multiplier, and a 16-bit barrel shifter. The SP-320 is designed to operate as a slave processor to a host general purpose computer in applications such as coherent integration of a radar return signal in multiple ranges, or dedicated FFT processing. Presently available is an I/O module conforming to the Intel Multichannel interface standard; other I/O modules will be designed to meet specific user requirements. The main processor board includes input and output FIFO (First In First Out) memories, both with depths of 4096 W, to permit asynchronous operation between the source of data and the host computer. This design permits burst data rates in excess of 5 MW/s.

Brosnahan, J. W.↗

NASA NTRS1984

A validation methodology for fault-tolerant clock synchronization

A validation method for the synchronization subsystem of a fault-tolerant computer system is presented. The high reliability requirement of flight crucial systems precludes the use of most traditional validation methods. The method presented utilizes formal design proof to uncover design and coding errors and experimentation to validate the assumptions of the design proof. The experimental method is described and illustrated by validating an experimental implementation of the Software Implemented Fault Tolerance (SIFT) clock synchronization algorithm. The design proof of the algorithm defines the maximum skew between any two nonfaulty clocks in the system in terms of theoretical upper bounds on certain system parameters. The quantile to which each parameter must be estimated is determined by a combinatorial analysis of the system reliability. The parameters are measured by direct and indirect means, and upper bounds are estimated. A nonparametric method based on an asymptotic property of the tail of a distribution is used to estimate the upper bound of a critical system parameter. Although the proof process is very costly, it is extremely valuable when validating the crucial synchronization subsystem.

Johnson, S. C.↗

NASA NTRS1985

Reliability and mass analysis of dynamic power conversion systems with parallel of standby redundancy

A combinatorial reliability approach is used to identify potential dynamic power conversion systems for space mission applications. A reliability and mass analysis is also performed, specifically for a 100 kWe nuclear Brayton power conversion system with parallel redundancy. Although this study is done for a reactor outlet temperature of 1100K, preliminary system mass estimates are also included for reactor outlet temperatures ranging up to 1500 K.

Juhasz, A. J.↗

NASA NTRS1985

Nonlinear optimal control with tensors - Some computational issues

Some computational issues associated with the calcualtion of optimal feedback controls for nonlinear systems in a tensor setting are described. The specific issues addressed pertain to the combinatorial nature of the loading of the elements into tensors used to represent the system, cost, and feedback, and the subsequent calculations involving these elements. Particular attention is given to: the symmetric tensor algebra which is a natural setting for representing polynomials; the conversions between symmetric and nonsymmetric tensors; the general nature of the calculations required; and the solution equation for nonlinear optimal feedback control. It is concluded that nonlinear tensor feedback can improve performance both in terms of system responses and in terms of system stability region.

Osullivan, J. A.↗