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At least 595 records · Page 33

All sources NASA NTRS DOE OSTI

DOE OSTI2010

THE EFFECT OF THE RADIAL PRESSURE GRADIENT IN PROTOPLANETARY DISKS ON PLANETESIMAL FORMATION

The streaming instability provides a promising mechanism for planetesimal formation because of its ability to concentrate solids into dense clumps. The degree of clumping strongly depends on the height-integrated solid to gas mass ratio Z in protoplanetary disks. In this Letter, we show that the magnitude of the radial pressure gradient that drives the streaming instability (characterized by {Pi} {identical_to} {eta}v{sub K} /c{sub s} , where {eta}v{sub K} is the reduction of Keplerian velocity due to the radial pressure gradient and c{sub s} is the sound speed) also strongly affects clumping. We present local two-dimensional hybrid numerical simulations of aerodynamically coupled particles and gas in the midplane of protoplanetary disks. Magnetic fields and particle self-gravity are ignored. We explore three different radial pressure gradient values appropriate for typical protoplanetary disks: {Pi} = 0.025, 0.05, and 0.1. For each {Pi} value, we consider four different particle size distributions ranging from submillimeter to meter sizes and run simulations with solid abundance from Z = 0.01 up to Z = 0.07. We find that a small radial pressure gradient strongly promotes particle clumping in that: (1) at fixed particle size distribution, the critical solid abundance Z {sub crit} above which particle clumping occurs monotonically increases with {Pi} and (2) at fixed Z, strong clumping can occur for smaller particles when {Pi} is smaller. Therefore, we expect planetesimals to form preferentially in regions of protoplanetary disks with a small radial pressure gradient.

79 ASTRONOMY AND ASTROPHYSICS↗

DOE OSTI2016

Accessing global data from accelerator devices

An aspect includes a table of contents (TOC) that was generated by a compiler being received at an accelerator device. The TOC includes an address of global data in a host memory space. The global data is copied from the address in the host memory space to an address in the device memory space. The address in the host memory space is obtained from the received TOC. The received TOC is updated to indicate that global data is stored at the address in the device memory space. A kernel that accesses the global data from the address in the device memory space is executed. The address in the device memory space is obtained based on contents of the updated TOC. When the executing is completed, the global data from the address in the device memory space is copied to the address in the host memory space.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2016

Accessing global data from accelerator devices

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Bit error protection in cache memories

A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

Bit error protection in cache memories

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Kalamatianos, John↗

DOE OSTI2017

CUDA Computation of the Feynman Distribution

In 2006, NVIDIA Corporation introduced the Computer Unified Device Architecture (CUDA) for C, C++, and Fortran programming languages. The CUDA parallel computing platform uses the Graphics Processing Unit (GPU) of NVIDIA graphics card, and it is designed for parallel computations. In these computations, the same algorithms are executed on the data in parallel. The GPU contains many Streaming Multiprocessors (SM) that can independently execute blocks of threads. A thread is a sequence of serial programmed instructions. The SM executes threads in groups of 32 and a group of 32 threads is called warp. The threads within a block can be synchronized and have access to a shared memory that is visible only to them. Conversely, blocks of threads cannot be synchronized and have access only to the global memory of the graphics card. This memory is called device memory and is independent of the host memory controlled by the Central Processing Unit (CPU). A single thread has access to a local memory (register) that is not visible to any other thread. The part of the program that is executed on the graphics card is called kernel. Each thread of the kernel has a unique identification index that is accessible by the in-built variable threadIdx; the latter is a 3-component vector. A threads block can contain up to 1024 threads. Blocks of threads have a unique identification index that is accessible by the in-built variable blockIdx; the latter is a 3-component vector. The in-built variable blockDim contains the number of threads per block; this variable is a 3-component vector. Threads and blocks represent different levels of parallelism; a kernel is executed as a grid of blocks of threads. Figure 1 illustrates a grid of thread blocks for a GPU with 2 SM. A SM can execute multiple blocks of threads in parallel; a block of threads is executed on a single SM. A GPU can execute multiple kernels concurrently. This work has used the Quadro M5000 graphics card with the following technical specifications: - 2048 cores with 861 MHz frequency, - 16 streaming multiprocessors, - 5.2 trillion transistors, - 8.2 Gb device memory, - 64 kb register memory (per thread), - 48 kb shared memory (per block) - 211.6 GB/s memory bandwidth, and - 3.5 GFLOPS floating point performance.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2014

Three-terminal resistive switching memory in a transparent vertical-configuration device

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

36 MATERIALS SCIENCE↗

NASA NTRS2010

NEPP non-volatile memory : FY09 summary report

This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for non-volatile memory (NVM) devices. The FY09 task was divided into two main efforts: 1. Development of in-house measurement capability for flash devices 2. Reliability characterization of multi-level vs. single-level flash devices The FY09 NEPP Non Volatile Memory study was organized into these two sections in recognition of the continued and increasing importance of NVM to NASA. All NASA missions use NVM for boot code storage and some limited data archiving. Space-grade NVM has lagged commercial NVM development by many orders of magnitude, however. This gap in density only continues to increase as space-grade memories remain constant in the 1–16 Mbit levels, while commercial flash-based devices shrink in size and double in capacity every 18 months. Commercial flash devices are now at the 32 Gbit level, 10,000 times denser than current NASA NVM. This FY marks the beginning of a significant technological transition in NVM for NASA. The aggressive scaling of commercial NVMs has, as a by-product, made some of the flash devices radiation-tolerant enough to be at least considered for low-level radiation environment missions [Irom 2008]. This NEPP task is focused on understanding the reliability and potential future applications of such highly scaled flash memories.

Heidecker, Jason↗

DOE OSTI2010

Multi-Level Bitmap Indexes for Flash Memory Storage

Due to their low access latency, high read speed, and power-efficient operation, flash memory storage devices are rapidly emerging as an attractive alternative to traditional magnetic storage devices. However, tests show that the most efficient indexing methods are not able to take advantage of the flash memory storage devices. In this paper, we present a set of multi-level bitmap indexes that can effectively take advantage of flash storage devices. These indexing methods use coarsely binned indexes to answer queries approximately, and then use finely binned indexes to refine the answers. Our new methods read significantly lower volumes of data at the expense of an increased disk access count, thus taking full advantage of the improved read speed and low access latency of flash devices. To demonstrate the advantage of these new indexes, we measure their performance on a number of storage systems using a standard data warehousing benchmark called the Set Query Benchmark. We observe that multi-level strategies on flash drives are up to 3 times faster than traditional indexing strategies on magnetic disk drives.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2010

Low latency counter event indication

A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding "interrupt arm" bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.

Gara, Alan G↗

DOE OSTI2011

MAGNETIC FLUX EXPULSION IN STAR FORMATION

Stars form in dense cores of magnetized molecular clouds. If the magnetic flux threading the cores is dragged into the stars, the stellar field would be orders of magnitude stronger than observed. This well-known 'magnetic flux problem' demands that most of the core magnetic flux be decoupled from the matter that enters the star. We carry out the first exploration of what happens to the decoupled magnetic flux in three dimensions, using a magnetohydrodynamic (MHD) version of the ENZO adaptive mesh refinement code. The field-matter decoupling is achieved through a sink particle treatment, which is needed to follow the protostellar accretion phase of star formation. We find that the accumulation of the decoupled flux near the accreting protostar leads to a magnetic pressure buildup. The high pressure is released anisotropically along the path of least resistance. It drives a low-density expanding region in which the decoupled magnetic flux is expelled. This decoupling-enabled magnetic structure has never been seen before in three-dimensional MHD simulations of star formation. It generates a strong asymmetry in the protostellar accretion flow, potentially giving a kick to the star. In the presence of an initial core rotation, the structure presents an obstacle to the formation of a rotationally supported disk, in addition to magnetic braking, by acting as a rigid magnetic wall that prevents the rotating gas from completing a full orbit around the central object. We conclude that the decoupled magnetic flux from the stellar matter can strongly affect the protostellar collapse dynamics.

79 ASTRONOMY AND ASTROPHYSICS↗

DOE OSTI2014

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

97 MATHEMATICS AND COMPUTING↗

NASA NTRS2018

Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

Li, Yue↗

NASA NTRS1993

Programmable DMA controller

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Hendry, David F.↗

DOE OSTI2014

Room temperature p-type conductivity and coexistence of ferroelectric order in ferromagnetic Li doped ZnO nanoparticles

Memory and switching devices acquired new materials which exhibit ferroelectric and ferromagnetic order simultaneously. We reported multiferroic behavior in Zn{sub 1−y}Li{sub y}O(0.00≤y≤0.10) nanoparticles. The analysis of transmission electron micrographs confirmed the hexagonal morphology and wurtzite crystalline structure. We investigated p-type conductivity in doped samples and measured hole carriers in range 2.4 × 10{sup 17}/cc to 7.3 × 10{sup 17}/cc for different Li contents. We found that hole carriers are responsible for long range order ferromagnetic coupling in Li doped samples. Room temperature ferroelectric hysteresis loops were observed in 8% and 10% Li doped samples. We demonstrated ferroelectric coercivity (remnant polarization) 2.5 kV/cm (0.11 μC/cm{sup 2}) and 2.8 kV/cm (0.15 μC/cm{sup 2}) for y = 0.08 and y = 0.10 samples. We propose that the mechanism of Li induced ferroelectricity in ZnO is due to indirect dipole interaction via hole carriers. We investigated that if the sample has hole carriers ≥5.3 × 10{sup 17}/cc, they can mediate the ferroelectricity. Ferroelectric and ferromagnetic measurements showed that higher electric polarization and larger magnetic moment is attained when the hole concentration is larger and vice versa. Our results confirmed the hole dependent coexistence of ferromagnetic and ferroelectric behavior at room temperature, which provide potential applications for switchable and memory devices.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

NASA NTRS1985

Electronic device aspects of neural network memories

The basic issues related to the electronic implementation of the neural network model (NNM) for content addressable memories are examined. A brief introduction to the principles of the NNM is followed by an analysis of the information storage of the neural network in the form of a binary connection matrix and the recall capability of such matrix memories based on a hardware simulation study. In addition, materials and device architecture issues involved in the future realization of such networks in VLSI-compatible ultrahigh-density memories are considered. A possible space application of such devices would be in the area of large-scale information storage without mechanical devices.

Lambe, J.↗

DOE OSTI2014

Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

A spintronic device, called the “strain assisted spin transfer torque (STT) random access memory (RAM),” is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗