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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 595 records · Page 33
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Direct-Sampling Beam Position Monitor (dsbpm) v1.0

Direct-Sampling Beam Position Monitor is an FPGA gateware and embedded firmware that run on evaluation kits (either Xilinx ZCU111 or Xilinx ZCU208 ) that digitizes signals up to 4GSPS and 4GHz analog bandwidth, which can be synchronized to the accelerator timing system, providing synchronous sampling frequency/phase digitization. In addition to these capabilities, a proof of concept for a beam position monitor is also present, providing an envelope detection algorithm capable of determining the transverse beam position for an electron circular accelerator, such as ALS/ALS-U.

Norum, William↗
DOE OSTI2022

Bantamweight Badger UDP support (BWUDP) v1.0

Software networking library to allow an FPGA ethernet core (such as Badger: https://gitlab.lbl.gov/hdl-libraries/bedrock/-/tree/master/badger) to be used in a soft-core processor or microcontroller.

Russo, Lucas↗
DOE OSTI2024

P38 heterogeneous multi-tiled system with support for message queues (MoSAIC) v0.1

The proposed system is written in the hardware description language (HDL) verilog targeting an FPGA board. It is intended as a testbed to explore architecture tradeoffs in multi-tiled heterogeneous architectures. Although we target FPGAs, the system can be implemented as a monolithic SoC or a package comprised of many chiplets that are interconnected in the same package using a NoC. The proposed NoC is lightweight and follows an axi-lite interface. The endpoints of the NoC are a heterogeneous mix of "tiles" as endpoints that are general purpose processors, fixed function accelerators, and programmable accelerators. We assume that the network interfaces for the NoC endpoints are all addressable in a global name-space in that they represent an address range (for memory addresses) or a range of unique identifiers that are associated with each individual tile. This makes the functionality abstract from the standpoint of the NoC design details. Message queues offer a direct inter-processor interface between peer general purpose cores and diverse accelerators that comprise an SoC. Although they share the same NoC infrastructure for inter-tile communication within an SoC or SiP, the hardware message queues bypass the memory hierarchy and thus do not pollute the memory state or invoke the cache coherence mechanism.

Gonzalez, LouisaPatricia↗
DOE OSTI2023

Quantum Instrumentation Control Kit Defect Arbitrary Waveform Generator (QICKDAWG) v.0

SAND2024-08598O The Quantum Instrumentation Control Kit Defect Arbitrary Waveform Generator (QICKDAWG) characterizes nitrogen-vacancy centers in diamond and other defects. It does this by using a radio frequency system-on-a-chip (RFSoC) field programmable gate array (FPGA). QICKDAWG synthesizes microwave pulses from the RFSoC to change the spin state of the defects. The software also allows for laser control using the RFSoC, which optically pumps defects. Ultimately, QICKDAWG supports the implementation of RFSoC FPGAs in defect characterization. This replaces the slow, expensive, traditional hardware, thus lowering the cost and time for defect characterization. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

SciDAC↗
DOE OSTI2024

USPAS Digital Low-Level RF firmware and software suite (uspas_llrf) v1.0

The USPAS Digital Low-Level RF firmware and software suite was originally developed for the USPAS 2023 LLRF course, for demonstrating the close loop RF control on the BerkeleyLab Marble FPGA carrier and Zest digitizer platform in controlling the RF field for various accelerators. The suite features Register-transfer level (RTL) designs for the board-support layer, digital signal processing and verification test benches, system-on-chip architecture, and Experimental Physics and Industrial Control System (EPICS) support, utilizing a open-source tool chain.

Du, Qiang↗
DOE OSTI2024

Sentinel

Network intrusion detection systems (NIDS) are commonplace in network security but they frequently employ algorithms that are computational demanding requiring hardware and software with significant power requirements. Two examples of such resource-intensive algorithms used for network security are regular expression matching and broader signature pattern matching which are commonly used in deep packet inspection (DPI). Network security algorithms that have large power requirements may be a challenge for low-power internet-of-things (IoT) environments, which generally lack the power resources to implement complex security measures like computationally expensive DPI at the edge. Furthermore, IoT environments incorporating 5G standalone networks have network latency constraints beyond just power that make DPI at the edge even more difficult. Programmable logic is ideally suited for machine learning inference for DPI because of its deep instruction level parallelism and single-cycle memory access. Machine learning approaches for DPI have been explored before using the programmable logic of field programmable gate arrays (FPGA) as a potential solution for NIDS approaches that would be power-suitable for IoT. However, those previous programmable logic NIDS approaches utilize either a supervised or unsupervised learning model. Sentinel utilizes the ensemble of these two machine learning approaches known as a semi-supervised approach which has shown promise in NIDS implementations. Sentinel provides a programmable logic implementation of a semi-supervised approach for DPI which operates at much lower power and latency than a GPU implementation with negligible loss of accuracy due to quantization through a logistic regressor.

Anderson, MatthewW [Idaho National Laboratory (INL↗
DOE OSTI2025

NeuroCoreX: Brain-Inspired Computing from Code to Circuit

NeuroCoreX is an open-source codebase that enables the implementation of brain-inspired, energy-efficient neuromorphic computing models on FPGA hardware. Designed to support real-time learning, all-to-all neural connectivity, and flexible network architectures, NeuroCoreX offers a hands-on, accessible platform for exploring biologically inspired models of neural computation. It empowers researchers, students, and developers to implement and experiment with adaptive systems—bringing the power of neuromorphic computing to a broader community through a low-cost, scalable, and reconfigurable framework.

Gautam, Ashish [Oak Ridge National Laboratory (ORN↗
DOE OSTI2024

Low duty cycle pulsed UV technique for spectroscopy of aluminum monochloride

We present what we believe to be a novel technique to minimize UV-induced damage in experiments that employ second-harmonic generation cavities. The principle of our approach is to reduce the duty cycle of the UV light as much as possible to prolong the lifetime of the used optics. The low duty cycle is achieved by ramping the cavity into resonance for a short time during the experimental cycle when the light is used and tuning it to an off-resonant state otherwise. The necessary fast ramp and length-stabilization control of the cavity is implemented with the FPGA-based STEMlab platform. We demonstrate the utility of this method by measuring the isotope shift of the electronic transition (X 1 Σ ← A 1 Π) in AlCl at 261.5 nm in a pulsed molecular beam experiment.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗
DOE OSTI2023

Disentangling Beam Losses in The Fermilab Main Injector Enclosure Using Real-Time Edge AI

The Fermilab Main Injector enclosure houses two accelerators, the Main Injector and Recycler Ring. During normal operation, high intensity proton beams exist simultaneously in both. The two accelerators share the same beam loss monitors (BLM) and monitoring system. Deciphering the origin of any of the 260 BLM readings is often difficult. The (Accelerator) Real-time Edge AI for Distributed Systems project, or READS, has developed an AI/ML model, and implemented it on fast FPGA hardware, that disentangles mixed beam losses and attributes probabilities to each BLM as to which machine(s) the loss originated from in real-time. The model inferences are then streamed to the Fermilab accelerator controls network (ACNET) where they are available for operators and experts alike to aid in tuning the machines.

43 PARTICLE ACCELERATORS↗
DOE OSTI2025

Redesign of the Timeline Generator at Fermilab using a web-based Flutter application, GraphQL API and an IOC

The control system at Fermilab is undergoing an evolution with a shift towards web-based applications with connections to the EPICS infrastructure. The Timeline Generator (TLG) is an application that serves to coordinate events across the lab using different timing links. These links include the Tevatron clock (TCLK), a 10 MHz serial link with events encoded at 20Hz and Machine Data (MDAT), a communication link with states encoded at 720Hz. This paper covers the redesign of the major components of the TLG. This includes a web-based Flutter application for building timelines. A placement service is in use that has a GraphQL interface and uses a timeline input to compute a schedule of events and states. The Flutter application sends this computed schedule to the TLG IOC via a GraphQL interface to the Data Pool Manager (DPM). The TLG IOC runs on an Arria FPGA, the Accelerator Clock Generator (ACLK-GEN), which is responsible for writing the events and states on to the different timing links.

Carmichael, Linden [Fermilab]↗
DOE OSTI2025

Proton pulse charge calculation algorithm in Beam Power Limiting System at Spallation Neutron Source

A proton pulse charge calculation algorithm in the Beam Power Limiting System (BPLS) at the Spallation Neutron Source (SNS) was developed and implemented in an FPGA. The algorithm calculates one-minute running average of the pulse charges and issues a fault to the Personal Protection System (PPS) and the Machine Protection System (MPS) when a limit is reached. A bit-accurate model of the algorithm was first developed and tested in Matlab® and then implemented and simulated in VHDL using Vivado® design environment. Finally, the algorithm was verified on a µTCA-based hardware platform.

Bobrek, Miljko [ORNL] (ORCID:0000000332763451)↗
DOE OSTI2021

Optimizing Mu2e Spill Regulation System Algorithms

A slow extraction system is being developed for the Fermilab’s Delivery Ring to deliver protons to the Mu2e experiment. During the extraction, the beam on target experiences small intensity variations owing to many factors. Various adaptive learning algorithms will be employed for beam regulation to achieve the required spill quality. We discuss here preliminary results of the slow and fast regulation algorithms validation through the computer simulations before their implementation in the FPGA. Particle tracking with sextupole resonance was used to determine the fine shape of the spill profile. Fast semi-analytical simulation schemes and Machine Learning models were used to optimize the fast regulation loop.

43 PARTICLE ACCELERATORS↗
DOE OSTI2021

JLAB LLRF 3.0 Development and Tests

The Jefferson Lab LLRF 3.0 system is being developed to replace legacy LLRF systems in the CEBAF accelerator. The new design builds upon 25 years of design and operational RF control experience, and our recent collaboration in the design of the LCLSII LLRF system. The new cavity control algorithm is a fully functional phase and amplitude locked Self Exciting Loop (SEL). This paper discusses the progress of the LLRF 3.0 hardware design, FPGA firmware development, User Datagram Protocol (UDP) operation, and recent LLRF 3.0 system tests on the CEBAF Booster cryomodule in the Upgrade Injector Test Facility (UITF).

Plawski, T. E.↗
DOE OSTI2021

Performance of the LLRF System for the Fermilab PIP-II Injector Test

PIP-II IT is a test facility for the PIP-II project where the injector, warm front-end, and the first two superconducting cryomodules are being tested. The 8-cavity half-wave-resonator (HWR) cryomodule operating at 162.5 MHz is followed by the 8-cavity single-spoke resonator(SSR1) cryomodule operating at 325 MHz. The LLRF systems for both cryomodules are based on a common SOC FPGA-based hardware platform. The resonance control systems for the two cryomodules are quite different, the first being a pneumatic system based on helium pressure and the latter a piezo/stepper motor type control. The data acquisition and control system can support both CW and Pulsed mode operations. Beam loading compensation is available which can be used for both manual/automatic control in the LLRF system. The user interfaces include EPICS, Labview, and ACNET. Testing of the RF system has progressed to the point of being ready for a 2 mA beam to be accelerated to 25 MeV. The design and performance of the field control and resonance control system operation with beam are presented in this paper.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

Synchronization and phase locking of resonant magnet power supplies for Mu2e experiment at Fermilab

The Mu2e Experiment has stringent beam structure requirements; namely, it requires short (~200 ns) proton bunches separated by 1.5-2.0 $\mu$s. This beam structure will be produced using the Fermilab 8 GeV Booster, the 8 GeV Recycler Ring, and the Delivery Ring, which was formerly part of the antiproton accumulator system. Out of time beam is limited to a fraction of level of no more than $1\times 10^{-10}$, a requirement known as "extinction". Achieving this level of extinction requires a system of resonant magnets and collimators, phased such that only in time particles will pass through. The Mu2e magnet system involves two components: a 300 kHz component, timed such that the 600 kHz beam will pass through the collimators at the nodes, and a 4.5 MHz system to reduce the slewing of the in-time beam. These two systems must be precisely phase locked to the bunch rate coming from the Delivery Ring, which itself must be phased to match beam transfers coming from the Recycler. This poster describes the control system for the magnets, which is based on an Intel Arria FPGA, which handles phase locking of the magnets to the Delivery Ring, including the phase jumps required to match transfers from the Recycler.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

Evaluation of the first version of the new RFPI system dedicated to PIP-II project accelerator

The Low-Level Radio Frequency (LLRF) control system is one of the most critical superconducting linac infrastructures responsible for the parameters of the beam acceleration. The LLRF system mainly focuses on the electromagnetic field parameters inside the cavity. While it incorporates fast feedback algorithms to optimize energy transfer to the passing particle beam it does not follow other cryomodule or cavity parameter changes. The Radio Frequency Protection Interlock (RFPI) system closely monitors various factors (like cryomodule vacuum, beamline vacuum, field emission probe current level, temperature, RF signal leakage, etc). Its simple but reliable logic has to provide an instant decision about the LLRF system or high-power amplifier output signal blocking in case of safety region excitation. This contribution presents a new version of the RFPI system which logic is implemented in the FPGA chip. The initial work on the prototype of the new system design resulted in the PoC (Proof of Concept) device. The PoC offers the possibility of various protection logic configurations, input signals parameters evaluation, and modularity aspects verification. The structure and test results from the device evaluation are summarized and discussed in this contribution.

43 PARTICLE ACCELERATORS↗