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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 577 records · Page 32
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

A New Class of SiC Power MOSFETs with Record-Low Resistance

Silicon carbide (SiC) power transistors are used in the main traction inverter of electric vehicles (EVs). Tesla began installing SiC power MOSFETs in 2017, and has now produced 4.8 million EVs containing over 169 million SiC power MOSFETs. Looking ahead, the worldwide EV market is projected to exceed 50 million vehicles per year by 2030 (Reuters, Oct. 25, 2022). This will create a demand for over two billion SiC power MOSFETs per year. Our program aims to double the efficiency of today's commercial power MOSFETs. This will cut the number of MOSFETs per EV in half, reducing cost, simplifying assembly, decreasing weight, and increasing vehicle reliability through reduced parts count. Our approach is to apply innovative design and advanced processing to increase the density of current-controlling channels in SiC power MOSFET. We have developed two new MOSFET devices, each of which increases the channel density by a factor of six over today's best commercial MOSFETs. This required implementing new fabrication processes, creating new device designs, and integrating the processing steps and device designs into a manufacturable technology. In this project we have developed two innovative devices: (i) a novel three-dimensional structure, the "tri-gate MOSFET," and (ii) a deeply-scaled, fully self-aligned trench MOSFET, the "IMOSFET". Both products were experimentally demonstrated during this project and meet the program goals of increased efficiency relative to the current state-of-the art commercial products. In the process we have generated significant IP, with two US patents issued and three applications pending. We have also published three journal articles and given reports on this technology at seven international conferences. The success of this program has led to significant follow-on funding from industry. In May 2023 Purdue University signed a five-year R&D contract with GlobalFoundries to transfer our novel technology to commercial production. With headquarters in Malta, NY, Global Foundries is one of the largest pure-play silicon foundries in the world, with annual revenue of $\$$8.1B. Their SiC foundry will be built around the next-generation 200-mm diameter SiC wafers, which will double the number of die per wafer and reduce per-die production cost.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Self-assembled Seashell Like Coatings for Large Area Robust Debris Shields for Next Generation Pulsed Power Drivers

During this LDRD project, our team developed a technology which enables the fabrication of novel nanostructures replicating seashell – “nature’s toughest material”. The resulting coatings exhibit high thermal stability up to 1650°C, which exceeds the hardness of Spectra® by ~44%, as well as the compressive strength of aluminum by ~57%. Coatings made with this technology are stronger, environmentally friendly, more sustainable, and more versatile than other comparable materials. Beryllium wafers, the current, most favorable shielding material in terms of thermal and mechanical properties, are very toxic and cost hundreds of times more than the new material developed in this project. The coatings on silicon wafer and stainless steel, respectively, have been tested as ride-along on the Z machine and clearly outperform the bare substrate. Use of this technology will have a profound global impact for pulsed power and fusion energy development, debris mitigation for spacecraft and satellites, durability of drill bits used in deep well drilling and tunnel boring operations, thermal protection of aircraft and manned spacecraft, and various other thermal and mechanical protection applications.

36 MATERIALS SCIENCE↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2024

MEMS RF accelerators for nuclear energy and advanced manufacturing

Energetic ions are widely used to develop radiation hard structural materials and fuels for advanced nuclear energy. Ion beams are also used to generate neutrons for nuclear materials testing, as well as in a series of high impact, high value adding manufacturing processes (ranging from doping of semiconductors to hardening of materials against wear and to increase bio-compatibility of materials). But to date, high power beams of high energy ions are simply too expensive because they are delivered from large single beam accelerators. We have recently demonstrated that MEMS technology enables massively parallel, low cost batch fabrication of ion beams. We propose to scale intense ion accelerators based on MEMS (micro-electro mechanical systems) to high beam power (>10 kW). With our approach, hundreds to thousands of ion beamlets will be densely packed on silicon wafers. Ions are injected and accelerated across gaps formed in stacks of wafers, leading to uniquely high current densities for intense ion accelerators with variable kinetic energy (0.1 to 10 MeV) and variable ion species. Our team brings together experts in high power ion accelerators from Lawrence Berkeley National Laboratory and leading experts in MEMS technology from Cornell University. We will deliver a disruptive technology of low cost, flexible and massively scalable ion accelerators that will enable the rapid development of radiation hard nuclear materials for advanced nuclear energy and enable new applications in manufacturing.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

Probing Boron Vacancy Complexes in h-BN Semi-Bulk Crystals Synthesized by Hydride Vapor Phase Epitaxy

Hexagonal BN (h-BN) has emerged as an important ultrawide bandgap (UWBG) semiconductor (Eg~6 eV). The crystal growth technologies for producing semi-bulk crystals/epilayers in large wafer sizes and understanding of defect properties lag decades behind conventional III-nitride wide bandgap (WBG) semiconductors. Here we report probing of boron vacancy (VB)-related defects in freestanding h-BN semi-bulk wafers synthesized by hydride vapor phase epitaxy (HVPE). A photocurrent excitation spectroscopy (PES) was designed to monitor the transport of photoexcited holes from deep-level acceptors. A dominant transition line at 1.66 eV with a side band near 1.62 eV has been directly observed, which matches well with the calculated energy levels of 1.65 for the VB-H deep acceptor in h-BN. The identification of VB complexes via PES measurement was further corroborated by the temperature-dependent dark resistivity and secondary ion mass spectrometry measurements. The results presented here suggested that it is necessary to focus on the optimization of V/III ratio during HVPE growth to minimize the generation of VB-related defects and to improve the overall material quality of h-BN semi-bulk crystals. The work also provided a better understanding of how VB complexes behave and affect the electronic and optical properties of h-BN.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Selective CW Laser Synthesis of MoS2 and Mixture of MoS2 and MoO2 from (NH4)2MoS4 Film

Very recently, the synthesis of 2D MoS2 and WS2 through pulsed laser-directed thermolysis can achieve wafer-scale and large-area structures, in ambient conditions. In this paper, we report the synthesis of MoS2 and MoS2 oxides from (NH4)2MoS4 film using a visible continuous-wave (CW) laser at 532 nm, instead of the infrared pulsed laser for the laser-directed thermolysis. The (NH4)2MoS4 film is prepared by dissolving its crystal powder in DI water, sonicating the solution, and dip-coating onto a glass slide. We observed a laser intensity threshold for the laser synthesis of MoS2, however, it occurred in a narrow laser intensity range. Above that range, a mixture of MoS2 and MoO2 is formed, which can be used for a memristor device, as demonstrated by other research groups. We did not observe a mixture of MoS2 and MoO3 in the laser thermolysis of (NH4)2MoS4. The laser synthesis of MoS2 in a line pattern is also achieved through laser scanning. Due to of the ease of CW beam steering and the fine control of laser intensities, this study can lead toward the CW laser-directed thermolysis of (NH4)2MoS4 film for the fast, non-vacuum, patternable, and wafer-scale synthesis of 2D MoS2.

(NH4)2MoS4↗
DOE OSTI2021

Characterization of CdZnTeSe Nuclear Detector Chemically Etched in Bromine Methanol

Semiconductor nuclear radiation detectors made from tertiary and quaternary compounds of cadmium telluride (CdTe) can operate at room temperature without cryogenic cooling. One of such materials that have become of great interest is cadmium zinc telluride selenide (CdZnTeSe). Compared to other CdTe-based materials, such as cadmium zinc telluride (CdZnTe), CdZnTeSe can be grown with much less Te inclusions and sub-grain boundary networks. Chemical etching is often used to smoothen wafer surfaces during detector fabrication. This paper presents the characterization of CdZnTeSe that is chemically etched using bromine methanol solution. Infrared imaging shows that the wafer has no sub-grain boundary networks that often limit detector performance. The current-voltage (I-V) characterization experiment gave a resistivity of 4.6 × 10 10 Ω-cm for the sample. The I-V curve was linear in the ±10 to ±50 volts range. An energy resolution of 7.2% was recorded at 100 V for the 59.6-keV gamma line of 241 Am.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1971

Mechanism of the oxidation of titanium disilicide.

Study of the oxidation of TiSi2 at temperatures of 300 to 1300 C. Wafers prepared using the techniques of powder metallurgy had densities of 95 to 98% of the theoretical value. On oxidation at temperatures up to 600 C, the polished wafers formed a protective, titania-silica glass. The rate data indicate a complex surface and diffusion-limited mechanism. Above 600 deg C, the oxide consisted of an amorphous SiO2 film with crystalline islands of TiO2 (rutile). From 1000 to 1300 C, parabolic kinetics with an activation energy of 21.3 kcal/mole were observed. These data are consistent with a model in which the rate-determining step is the diffusion of oxygen through the silica film with the simultaneous diffusion of titanium from the substrate to the islands of rutile growing on top of the amorphous silica.

Schwettmann, F. N.↗
NASA NTRS1972

Techniques for control of long-term reliability of complex integrated circuits. I - Reliability assurance by test vehicle qualification.

Development of an alternate approach to the conventional methods of reliability assurance for large-scale integrated circuits. The product treated is a large-scale T squared L array designed for space applications. The concept used is that of qualification of product by evaluation of the basic processing used in fabricating the product, providing an insight into its potential reliability. Test vehicles are described which enable evaluation of device characteristics, surface condition, and various parameters of the two-level metallization system used. Evaluation of these test vehicles is performed on a lot qualification basis, with the lot consisting of one wafer. Assembled test vehicles are evaluated by high temperature stress at 300 C for short time durations. Stressing at these temperatures provides a rapid method of evaluation and permits a go/no go decision to be made on the wafer lot in a timely fashion.

Van Vonno, N. W.↗
NASA NTRS1972

A millimeter wave mixer

The mixer consists of a small metallic wafer, in which are embedded the semiconductor diodes, the waveguide mount is used to couple the diode wafer to the signal circuit, an RF tuning element, and a 3 mm coaxial connector for the IF output terminal. The cross-sectional dimension is that of the waveguide flange (19 mm x 19 mm, 0.75" x 0.75"), the overall length is nominally 25 mm (1.0 inch). This component is to be used as a single-ended RF mixer with four replacement mixer diodes, operating in the three millimeter wavelength band.

Dickens, L. E.↗
NASA NTRS1973

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

Bullis, W. M.↗
NASA NTRS1973

Study for identification of beneficial uses of Space, phase 1. Volume 2, book 2: Technical report: results, conclusions and recommendations

A variety of technologies were investigated to determine the benefits to be derived from space activities. The subjects accepted for product development are: (1) eutectics for cold cathodes, (2) higher putiry fiber optics, (3) fluidic wafers, (4) large germanium wafers for gamma ray camera, (5) improved batteries and capacitors, (6) optical filters, (7) corrosion resistant electrodes, (8) high strength carbon-based filaments for plastic reinforcement, and (9) new antibiotics. In addition, three ideas for services, involving disposal of radioactive wastes, blood analysis, and enhanced solar insolation were proposed.

Source record↗
NASA NTRS1974

Gravitational effects of process-induced dislocations in silicon

Matters pertaining to semiconductor device fabrication were studied in terms of the influence of gravity on the production of dislocations in silicon wafers during thermal cycling in a controlled ambient where no impurities are present and oxidation is minimal. Both n-type and p-type silicon wafers having a diameter of 1.25 in to 1.5 in, with fixed orientation and resistivity values, were used. The surface dislocation densities were measured quantitatively by the Sirtl etch technique. The results show two significant features of the plastic flow phenomenon as it is related to gravitational stress: (1) the density of dislocations generated during a given thermal cycle is directly related to the duration of the cycle; and (2) the duration of the thermal cycle required to produce a given dislocation density is inversely related to the equilibrium temperature. Analysis of the results indicates that gravitational stress is instrumental in process-induced defect generation.

Porter, W. A.↗
NASA NTRS1974

Gravitational effects on process-induced defects in single crystal silicon

Description and discussion of a series of experiments which vary each of several important processing parameters including wafer orientation, temperature, gravity greater than 1 g, and ultimately zero gravity. These experiments are in progress and results to date are included from experiments which control temperature, duration of thermal cycle, and wafer orientation during 1 g processing. Preliminary evidence is presented which indicates that gravitational stresses play a role in defect generation during processing at 1 g.

Porter, W. A.↗
NASA NTRS1975

Summary of theoretical and experimental investigation of grating type, silicon photovoltaic cells

Theoretical and experimental aspects are summarized for single crystal, silicon photovoltaic devices made by forming a grating pattern of p/n junctions on the light receiving surface of the base crystal. Based on the general semiconductor equations, a mathematical description is presented for the photovoltaic properties of such grating-like structures in a two dimensional form. The resulting second order elliptical equation is solved by computer modeling to give solutions for various, reasonable, initial values of bulk resistivity, excess carrier concentration, and surface recombination velocity. The validity of the computer model is established by comparison with p/n devices produced by alloying an aluminum grating pattern into the surface of n-type silicon wafers. Current voltage characteristics and spectral response curves are presented for cells of this type constructed on wafers of different resistivities and orientations.

Chen, L. Y.↗
NASA NTRS1975

Electrical characterization of GaAs single crystal in direct support of M555 flight experiment

The exploration of several nondestructive methods of electrical characterization of semiconductor single crystals was carried out during the period ending May 1974. Two methods of obtaining the microwave skin depth, one for the mapping flat surfaces and the other for analyzing the whole surface of small single crystal wafers, were developed to the stage of working laboratory procedures. The preliminary 35 GHz data characterizing the two types of space-related single crystal surfaces, flat slices of gallium arsenide and small wafers of germanium selenide, are discussed. A third method of nondestructive mapping of donor impurity density in semiconductor surfaces by scanning with a light beam was developed for GaAs; its testing indicates reasonable precision at reasonable scan rates for GaAs surfaces at room temperature.

Castle, J. G.↗
NASA NTRS1975

Electrical characterization of GaAs single crystal in direct support of M555 flight experiment

An exploration of several nondestructive methods of electrical characterization of semiconductor single crystals was carried out. Two methods of obtaining the microwave skin depth, one for mapping flat surfaces and the other for analyzing the whole surface of small single crystal wafers, were developed to the stage of working laboratory procedures. The preliminary 35 GHz data characterizing the two types of space related single crystal surfaces, flat slices of gallium arsenide and small wafers of germanium selenide, are discussed. A third method of nondestructive mapping of donor impurity density in semiconductor surfaces by scanning with a light beam was developed for GaAs; its testing indicates reasonable precision at reasonable scan rates for GaAs surfaces at room temperature.

Castle, J. G.↗
NASA NTRS1977

Assessment of present state-of-the-art sawing technology of large diameter ingots for solar sheet material

The objective of this program is to assess the present state-of-the-art sawing technology of large diameter silicon ingots (3 inch and 4 inch diameter) for solar sheet materials. During this period, work has progressed in three areas: (1) slicing of the ingots with the multiblade slurry saw and the I.D. saw, (2) characterization of the sliced wafers, and (3) analysis of direct labor, expendable material costs, and wafer productivity.

Yoo, H. I.↗