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At least 577 records · Page 32

Polyurethane Microparticles for Stimuli Response and Reduced Oxidative Degradation in Highly Porous Shape Memory Polymers

Shape memory polymers (SMPs) have been found to be promising biomaterials for a variety of medical applications; however, the clinical translation of such technology is dependent on tailorable properties such as gravimetric changes in degradation environments. For SMPs synthesized from amino-alcohols, oxidation resulting in rapid mass loss may be problematic in terms of loss of material functionality as well as toxicity and cytocompatibility concerns. Control of gravimetric changes was achieved through the incorporation of small molecule antioxidants, either directly into the polymer matrix or included in microparticles to form a SMP composite material. Direct incorporation of small molecule antioxidants, such as phenolic alcohols, was found to alter shape memory attributes and increase elastic modulus at the expense of the strain to failure. Such changes could not ensure retention of the antioxidants and therefore did not increase oxidative stability. However, the inclusion of antioxidants in microparticles was found to produce materials with similar thermomechanical and shape memory properties while increasing oxidative resistance compared to controls. The microparticle composite SMPs also act as a platform for environmental sensing, such as pH-dependent fluorescence shifts and payload release, as demonstrated by fluorescent dyes and the release of antioxidants. The use of polyurethane-urea microparticles in porous SMPs is demonstrated to increase biostability of the materials, by approximately 25%, and ultimately extend their lifespan for use in aneurysm occlusion as determined through calculated in vivo degradation rates corresponding to a porcine aneurysm environment.

Weems, A. C.↗

Total Ionizing Dose Response of SDRAM, DDR2 and DDR3 Memories

Total Ionizing Dose response (ID) of SDRAM (Synchronous Dynamic Random Access Memory), DDR2 (Double Data Rate2) and DDR3 (Double Data Rate3) memories is reported in static bias, and auto refresh modes. Data analysis reveals some types of memory have significant increases in stuck bits during TID exposure when refreshed.

Amrbar, Mehran↗

A radiation - tolerant, low - power non - volatile memory based on silicon nanocrystal quantum dots.

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in Si02 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled.

Green, M. L.↗

Radiation tests of highly scaled, high-density, commercial, nonvolatile NAND flash memories— update 2012

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Allen, Gregory R.↗

Meta-aerogels: Auxetic Shape-memory Polyurethane Aerogels

Shape-memory poly(isocyanurate-urethane) (PIR-PUR) aerogels are low-density monolithic nanoporous solids that remember and return to their permanent shape through a heating actuation step. Herein, through structural design at the macro scale, the shape-memory response is augmented with an auxetic effect manifested by a negative Poisson’s ratio of approximately -0.8 at 15% compressive strain. Thus, auxetic shape-memory PIR-PUR monoliths experience volume contraction upon compression at a temperature above the glass transition temperature of the base polymer (Tg ~ 30 °C), and they can be stowed indefinitely in that temporary shape by cooling below Tg. By heating back above Tg, the compressed/shrunk form expands back to their original shape/size. This technology is relevant to a broad range of industries spanning the commercial, aeronautical, and aerospace sectors. The materials are referred to as meta-aerogels and their potential applications include minimally invasive medical devices, soft robotics, and in situations where volume is at a premium, as for example for storage of deployable space structures and planetary habitats during transport to the point of service.

Sadeq Malakooti↗

Shape memory polymer foams for endovascular therapies

A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding the physical anomaly. The shape memory material body has a primary shape for occluding the physical anomaly and a secondary shape for being positioned in the physical anomaly.

59 BASIC BIOLOGICAL SCIENCES↗

TriC: Distributed-memory Triangle Counting by Exploiting the Graph Structure

Graph analytics has emerged as an important tool in the analysis of large scale data from diverse application domains such as social networks, cyber security and bioinformatics. Counting the number of triangles in a graph is a fundamental kernel with several applications such as detecting the community structure of a graph or in identifying important vertices in a graph. The ubiquity of massive datasets is driving the need to scale graph analytics on parallel systems. However, numerous challenges exist in efficiently parallelizing graph algorithms, especially on distributed-memory systems. Irregular memory accesses and communication patterns, low computation to communication ratios, and the need for frequent synchronization are some of the leading challenges. In this paper, we present TriC, our distributed-memory implementation of triangle counting in graphs using the Message Passing Interface (MPI), as a submission to the 2020 GraphChallenge competition. Using a set of synthetic and real-world inputs from the challenge, we demonstrate a speedup of up to 90x relative to previous work on 32 processor-cores of a NERSC Cori node. We also provide details from distributed runs with up to8192 processes along with strong scaling results. The observations presented in this work provide an understanding of the system-level bottlenecks at scale that specifically impact sparse-irregular workloads and will therefore benefit other efforts to parallelize graph algorithms.

Halappanavar, Mahantesh↗

Memory page access counts based on page refresh

A processing system tracks counts of accesses to memory pages using a set of counters located at the memory module that stores the pages, wherein the counts are adjusted at least in part based on refreshes of the memory pages. This approach allows a processing system to efficiently maintain the counts with relatively small counters and with relatively low overhead. Furthermore, the rate at which the counters are adjusted, relative to the page refreshes, is adjustable, so that the access counts are useful for a wide variety of application types.

97 MATHEMATICS AND COMPUTING↗

Athena: High-Performance Sparse Tensor Contraction Sequence on Heterogeneous Memory

Sparse tensor contraction sequence has been widely employed in many fields, such as chemistry and physics. However, how to efficiently implement the sequence faces multiple challenges, such as redundant computations and memory operations, massive memory consumption, and inefficient utilization of hardware. To address the above challenges, we introduce Athena, a high-performance framework for SpTC sequences. Athena introduces new data structures, leverages emerging Optane-based heterogeneous memory (HM) architecture, and stage parallelism. In particular, Athena introduces shared hash table-represented sparse accumulator to eliminate unnecessary input processing and data migration; Athena uses a novel data-semantic guided dynamic migration solution to make the best use of the Optane-based HM for high performance; Athena also co-runs execution phases with different characteristics to enable high hardware utilization. Evaluating with 12 datasets, we show that Athena brings 327-7362× speedup over the state-of-the-art SpTC algorithm. With the dynamic data placement guided by data semantics, Athena brings performance improvement on Optane-based HM over a state-of-the-art software-based data management solution, a hardware-based data management solution, and PMM-only by 1.58×, 1.82×, and 2.34× respectively.

Liu, Jiawen↗

Flexible optimized data handling in systems with multiple memories

Methods and systems for optimizing an application for a computing system having multiple distinct memory locations that are interconnected by one or more communication channels include determining one or more data handling properties for a data region in an application. One or more data handling policies for the data region are determined based on the one or more data handling properties. Data setup costs are determined for a scope in the application that uses the data region in different memory locations based on the one or more data handling properties. The application is optimized in accordance with the one or more data handling policies and the data setup costs for the different memory locations.

Chen, Tong↗

Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers

A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

Kalamatianos, John↗

Comparing LLC-Memory Traffic between CPU and GPU Architectures

The cache hierarchy in modern CPUs and GPUs is becoming increasingly complex, which makes understanding the handshake between the memory access patterns and the cache hierarchy difficult. Moreover, the details of different cache policies are not publicly available. Therefore, the research community relies on observation to understand the relationship between memory access patterns and cache hierarchy. Our previous studies delved into the different microarchitectures of Intel CPUs. In this study, GPUs from NVIDIA and AMD are considered. Even though the execution models in CPUs and GPUs are distinct, this study attempts to correlate the behavior of the cache hierarchy of CPUs and GPUs. Using the knowledge gathered from studying Intel CPUs, the similarities and dissimilarities between CPUs and GPUs are identified. Through model evaluation, this study provides a proof of concept that traffic between last-level cache and memory can be predicted for sequential streaming and strided access patterns on GPUs.

Monil, M. A. H.↗

Antiferromagnetic memory storage devices from magnetic transition metal dichalcogenides

Switchable antiferromagnetic (AFM) memory devices are provided based on magnetically intercalated transition metal dichalcogenides (TMDs) of the form AxMC2, where A is a magnetic element of stoichiometry x between 0 and 1, M is a transition metal of stoichiometry 1, and C is a chalcogen of stoichiometry 2. Memory storage is achieved by fabricating these materials into crosses of two or more bars and driving DC current pulses along the bars to rotate the AFM order to a fixed angle with respect to the current pulse. Application of current pulses along different bars can switch the AFM order between multiple directions. Standard resistance measurements can detect the orientation of the AFM order as high or low resistance states. The state of the device can be set by the input current pulses, and read-out by the resistance measurement, forming a non-volatile, AFM memory storage bit.

Analytis, James G.↗

Shape memory polymer foams for endovascular therapies

A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding the physical anomaly. The shape memory material body has a primary shape for occluding the physical anomaly and a secondary shape for being positioned in the physical anomaly.

59 BASIC BIOLOGICAL SCIENCES↗

Flexible optimized data handling in systems with multiple memories

Methods and systems for optimizing an application for a computing system having multiple distinct memory locations that are interconnected by one or more communication channels include determining one or more data handling properties for a data region in an application. One or more data handling policies for the data region are determined based on the one or more data handling properties. Data setup costs are determined for a scope in the application that uses the data region in different memory locations based on the one or more data handling properties. The application is optimized in accordance with the one or more data handling policies and the data setup costs for the different memory locations.

Chen, Tong↗

High-Speed Ionic Synaptic Memory Based on 2D Titanium Carbide MXene

Synaptic devices with linear high-speed switching can accelerate learning in artificial neural networks (ANNs) embodied in hardware. Conventional resistive memories however suffer from high write noise and asymmetric conductance tuning, preventing parallel programming of ANN arrays. Electrochemical random-access memories (ECRAMs), where resistive switching occurs by ion insertion into a redox-active channel, aim to address these challenges due to their linear switching and low noise. ECRAMs using 2D materials and metal oxides however suffer from slow ion kinetics, whereas organic ECRAMs enable high-speed operation but face challenges toward on-chip integration due to poor temperature stability of polymers. Here, ECRAMs using 2D titanium carbide (Ti 3 C 2 T x ) MXene that combine the high speed of organics and the integration compatibility of inorganic materials in a single high-performance device are demonstrated. These ECRAMs combine the speed, linearity, write noise, switching energy, and endurance metrics essential for parallel acceleration of ANNs, and importantly, they are stable after heat treatment needed for back-end-of-line integration with Si electronics. The high speed and performance of these ECRAMs introduces MXenes, a large family of 2D carbides and nitrides with more than 30 stoichiometric compositions synthesized to date, as promising candidates for devices operating at the nexus of electrochemistry and electronics.

2D materials↗

Distributed Quantum Computing with Photons and Atomic Memories

The promise of universal quantum computing requires scalable single- and inter-qubit control interactions. Currently, three of the leading candidate platforms for quantum computing are based on superconducting circuits, trapped ions, and neutral atom arrays. However, these systems have strong interaction with environmental and control noises that introduce decoherence of qubit states and gate operations. Alternatively, photons are well decoupled from the environment and have advantages of speed and timing for quantum computing. Photonic systems have already demonstrated capability for solving specific intractable problems like Boson sampling, but face challenges for practically scalable universal quantum computing solutions because it is extremely difficult for a single photon to “talk” to another deterministically. Here, a universal distributed quantum computing scheme based on photons and atomic-ensemble-based quantum memories is proposed. Taking the established photonic advantages, two-qubit nonlinear interaction is mediated by converting photonic qubits into quantum memory states and employing Rydberg blockade for the controlled gate operation. Spatial and temporal scalability of this scheme is demonstrated further. Furthermore, these results show photon-atom network hybrid approach can be a potential solution to universal distributed quantum computing.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Progress toward picosecond on-chip magnetic memory

Here, we offer a perspective on the prospects of ultrafast spintronics and opto-magnetism as a pathway to high-performance, energy-efficient, and non-volatile embedded memory in digital integrated circuit applications. Conventional spintronic devices, such as spin-transfer-torque magnetic-resistive random-access memory (STT-MRAM) and spin–orbit torque MRAM, are promising due to their non-volatility, energy-efficiency, and high endurance. STT-MRAMs are now entering into the commercial market; however, they are limited in write speed to the nanosecond timescale. Improvement in the write speed of spintronic devices can significantly increase their usefulness as viable alternatives to the existing CMOS-based devices. In this article, we discuss recent studies that advance the field of ultrafast spintronics and opto-magnetism. An optimized ferromagnet–ferrimagnet exchange-coupled magnetic stack, which can serve as the free layer of a magnetic tunnel junction (MTJ), can be optically switched in as fast as ~3 ps. Integration of ultrafast magnetic switching of a similar stack into an MTJ device has enabled electrical readout of the switched state using a relatively larger tunneling magnetoresistance ratio. Purely electronic ultrafast spin–orbit torque induced switching of a ferromagnet has been demonstrated using ~6 ps long charge current pulses. We conclude our Perspective by discussing some of the challenges that remain to be addressed to accelerate ultrafast spintronics technologies toward practical implementation in high-performance digital information processing systems.

42 ENGINEERING↗