Low Cost Contacts and Interconnects for Thin Film Solar
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14 SOLAR ENERGY↗
SEARCH · Engineering Papers
Results for “interconnections”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Indium Interconnect Mechanical Performance with Variable UBM and Decreasing Bump Size .
Abstract not provided.
Wheeling, Rebecca↗
Electricity Grid Capacity Expansion Planning Considering Interconnection Queue Uncertainty
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Engineering - Power transmission and distribution,↗
Enabling Interconnected Science Workflows through an Adapter Approach
The INTERSECT Software framework project aims to create an open federated library that connects, coordinates, and controls systems in the scientific domain. It features the Adapter, a flexible and extensible interface inspired by the Adapter design pattern in object-oriented programming. By utilizing Adapters, the INTERSECT SDK enables effective communication and coordination within a diverse ecosystem of systems. This adaptability facilitates the execution of complex operations within the framework, promoting collaboration and efficient workflow management in scientific research. Additionally, the generalizability of Adapters and their patterns enhances their utility in other scientific software projects and challenges.
McGaha, Jesse↗
Flexible Superconducting Interconnects Realized by Electrodeposition of Rhenium on an Aerosol Jet Printed Seed Layer
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Manzi, Jacob Richard [Sandia National Laboratories↗
A Review of the Current Landscape of Distributed Wind Interconnection Standards
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Louie, Melissa (ORCID:0009000846036427)↗
Low Cost (CAPEX and variable): Tool design for cell and module fabrication with thin, free-standing silicon wafers
This project aimed to develop technologies that can potentially enable free-standing thin (<80 μm) wafer in today’s manufacturing lines with high production yield, and thereby reduce capex barriers of silicon photovoltaics cells and modules. One of the major benefits is that thin wafer dramatically reduces the amount of polysilicon required. As a result, it can lead to reduction in the capital expenditures associated with polysilicon refining and wafer fabrication, which together are more than half of the total capital expenditure to manufacture Si PV module. We focused our efforts on developing the tools needed to enable high yield fabrication of wafer, cell, and module with thin silicon wafers. However, as the wafer thickness reduces, the major challenge is that wafer breakage increases significantly. Three technological areas were explored in this project to improve the production yield of the silicon wafer, namely detection of edge cracks via dark-field near-infrared (NIR) scattering; (2) wafer handling using controlled temperature profiles; (3) manufacturable low-stress cell interconnection for multiwire. First, the formation of wafer cracks in submillimeter length is one of the reasons that causes wafer breakages. Crack detection tools are needed to enable us to locate and track the wafer crack during manufacturing, so that we can improve the process to reduce initialization. The state-of-the-art crack detection technique cannot fulfill the need for measuring submillimeter edge cracks detrimental for thin wafers. The prototype developed in this project demonstrates the scanning of microcracks near wafer edges. With a semi-automatic laboratory setup, the submillimeter cracks were reliably detected near the edges in multi-Si wafers. The smallest detectable crack is 200 µm in length in slow scans; and submillimeter cracks are detected in high-throughput scans at the scan speed of >0.5 m/s, which is compatible with the inline detection of a manufacturing line at least 1 sec/wafer. This detection limit is a significant advancement in comparison to the benchmarked industrial tool. Second, wafer handling with the well-controlled temperature profile was thought to be the solution to reduce crack initiation and propagation during the manufacturing. However, without crack detection being widely adopted in production line, we did not find a strong industrial pull toward this technology. We did an initial literature survey and then diverted our efforts to the other tasks. Third, the innovation on low-stress multi-wire interconnection tackles a fundamental problem in the standard interconnection scheme. The standard over-under “zig-zag” interconnection induces a significant amount of stress into the soldering point on the cell whenever PV module is under stress, e.g., thermal cycling, transportation, and installation. Therefore, the interconnection process was re-designed in this project to allow for significant movement between adjacent solar cells, e.g., due to thermal expansion, without building up stresses on the solar cells or solder joints. The new interconnection method with the cross-connect wire also simplifies the tabbing and stringing process by replacing the standard over-under method with an off-cell interconnect from top to bottom. A manual tabbing and stringing tool for this new process was prototyped in the lab to demonstrate the fabrication of this new interconnection design. During the test with brass sheets as our “testing cells”, it was found that the mechanical cycling test only broke the interconnection after more than 50,000 cycles, which is equivalent to more than 130 years of the day-and-night thermal cycles. Lastly, throughout the project, we continuously analyzed the PV market with techno-economic analysis to identify the opportunity for thin Si adoption. Even though the drastic cost reduction has already happened in the past five years, our analysis results indicated that we can still save quite significantly in both manufacturing cost and factory capex, Particularly, in order to grow the PV manufacturing capacity to multi-terawatt level, reducing the thickness of silicon wafer is one of the most effective ways to quickly reduce factory capex, and sustain the high growth rate. The technologies developed in this project are readily available to provide some assistances in tackling the production yield problem.
14 SOLAR ENERGY↗
Grid connection barriers to renewable energy deployment in the United States
Bulk-power grid connection is an emerging bottleneck to the entry of wind, solar, and storage but has been understudied due to a lack of data. We create and analyze two novel interconnection datasets with more than 38,000 project-level observations that provide new information documenting interconnection challenges in the United States. Active grid connection requests are more than double the total installed capacity of the US power plant fleet (2,600 vs. 1,280 GW). The time required to secure a connection has increased by 70% over the last decade, and withdrawal rates remain high at 80%, suggesting a constrained transmission system that jeopardizes energy transition targets. Wide distributions of interconnection costs indicate the inherent uncertainty of the interconnection process. Interconnection requests that identify large transmission upgrades tend to withdraw from the process. These findings suggest the need for interconnection reforms, tighter links between long-term transmission planning and project-level interconnection processes, and more interconnection outcome transparency.
29 ENERGY PLANNING, POLICY, AND ECONOMY↗
CERF: IM3 Projected Western US Power Plant Locations
Overview The Capacity Expansion Regional Feasibility (CERF) model is an open-source geospatial python package that provides new power plant locations at a 1km resolution. The model ingests U.S. state or regional-scale electricity system capacity expansion plans, such as those produced by the Global Change Analysis Model (GCAM-USA), and identifies feasible, site-specific locations for individual new power plants (renewable and non-renewable). CERF combines high-resolution geospatial suitability analyses with an economic algorithm that selects individual plant siting locations based on grid interconnection costs and the locational marginal value of new generation. The model incorporates a wide range of dynamic constraints and opportunities, such as protected lands, population density, existing infrastructure, and water availability. This dataset provides CERF power plant siting results for IM3 Phase 2 simulations across eight different scenarios for the Western US through 2055. The scenarios include combinations of two Shared Socioeconomic Pathways (SSP3 and SSP5) with four high-resolution climate projections specific to the United States (see, https://tgw-data.msdlive.org/). These climate projections include "hotter" and "cooler" variants for two Representative Concentration Pathways (RCP4.5 and RCP8.5). The resulting eight simulations are: rcp45cooler_ssp3 rcp45cooler_ssp5 rcp45hotter_ssp3 rcp45hotter_ssp5 rcp85cooler_ssp3 rcp85cooler_ssp5 rcp85hotter_ssp3 rcp85hotter_ssp5 CERF siting results in this dataset correspond to capacity expansion plans in the GCAM-USA IM3 Phase 2 simulation data and are available for each of the above scenarios. Data Details Temporal Range: 2015-2055 in 5-year timesteps. Note that 2015 is the experiment base year and 2020 and beyond represent model simulation years. Spatial Range: Plant locations are provided for the eleven states in the Western US including Arizona, California, Colorado, Idaho, Montana, New Mexico, Nevada, Oregon, Utah, Washington, and Wyoming. Spatial Resolution: 1 km-squared, provided in x and y coordinates Geospatial Projection: Albers Equal Area Conic (ESRI:102003) File Type: csv The dataset contains subdirectories for each of the eight scenarios described in the overview. Each scenario folder contains two subfolders with the following information: 1. Power Plant Data This directory contains a single .csv file of power plant locations for both pre-existing (non-CERF sited plants in operation in 2015) and new (CERF-sited) power plants across the temporal range along with additional CERF model output parameters for CERF-sited plants. Plant with a siting year earlier than 2020 correspond to facilities that are operational leading into the first timestep CERF simulation. For a more detailed description of CERF model output parameters, see the CERF model documentation. Note that the cerf_plant_id parameter is unique within each scenario file but not across scenario files. Parameter Descriptions scenario - Name of scenario cerf_plant_id - Unique siting identifier cerf_sited - If True, indicates that plant was sited by CERF model. If False, indicates pre-existing facility region_name - Name of region (state) tech_id - Technology ID tech_name - Full generation technology name inclusive of cooling type (if applicable) and additional characteristics tech_simple - Simplified generation technology type unit_size_mw - Power plant unit size (MW) xcoord - X coordinate in the default CRS (meters) ycoord - Y coordinate in the default CRS (meters) index - Index position in the flattend 2D array buffer_in_km - Exclusion buffer around site (km) sited_year - Year of siting retirement_year - Year of retirement lmp_zone - Locational marginal price (LMP) zone ID locational_marginal_price_usd_per_mwh - Locational marginal price ($/MWh) generation_mwh_per_year - Generation output (MWh/yr) operating_cost_usd_per_year - Cost of plant operations ($/yr) net_operational_value - Net operational value based on LMP and and operating costs ($/yr) interconnection_cost - Cost of interconnection for transmission & gas pipeline (if applicable) net_locational_cost -- Difference of interconnection cost and operating value ($/yr) capacity_factor_fraction - Capacity factor (fraction) carbon_capture_rate_fraction - Carbon capture rate (fraction) fuel_co2_content_tons_per_btu - Fuel CO2 content (tons/Btu) fuel_price_usd_per_mmbtu - Fuel price ($/MMBtu) fuel_price_esc_rate_fraction - Fuel price escalation rate (fraction) heat_rate_btu_per_kWh - Heat rate (Btu/kWh) lifetime_yrs - Technology lifetime for annuity (years) operational_life_yrs - Operational lifetime for retirement (years) variable_om_usd_per_mwh - Variable operation and maintenance costs of yearly capacity use ($/MWh) variable_om_esc_rate_fraction - Variable operation and maintenance costs escalation rate (fraction) carbon_tax_usd_per_ton - Carbon tax ($/ton) carbon_tax_esc_rate_fraction - Carbon tax escalation rate (fraction) 2. Storage Data This directory contains information on new and pre-existing energy storage facilities operational in each timestep along with various storage operational parameters. The 2015 timestep provides pre-existing energy storage data and corresponds with facilities that are operational leading into the first model simulation timestep. Note that coordinates in the storage files correspond to the interconnection point on the grid (substation location), not individual energy storage locations. Energy storage is added in a cumulative process at each given interconnection point. That is, each individual file provides the total operational storage capacity interconnected to the specified substation for the given timestep, inclusive of previously installed storage at that location and new storage installed in that timestep at that location. Parameters scenario - Name of scenario timestep - Simulation timestep name - Unique storage identifier s_typ - Type of energy storage technology (battery or pumped storage hydro) s_node - Node ID of interconnecting substation xcoord - X coordinate in the default CRS (meters) ycoord - Y coordinate in the default CRS (meters) charge_rate - Maximum charge rate (power capacity) of storage system (MW) discharge_rate - Maximum discharge rate (power capacity) of storage system (MW) duration - Duration of storage system (hours) max_SoC - Allowed maximum state of charge (energy capacity) of storage system (MWh) min_SoC -Allowed minimum state of charge (energy capacity) of storage system (MWh) charge_eff - Efficiency of charge (fraction between 0 and 1) discharge_eff - Efficiency of discharge (fraction between 0 and 1) Acknowledgment IM3 is a multi-institutional effort led by Pacific Northwest National Laboratory and supported by the U.S. Department of Energy's Office of Science as part of research in MultiSector Dynamics, Earth and Environmental Systems Modeling Program.
CERF↗
Advanced Flip Chips in Extreme Temperature Environments
The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.
Ramesham, Rajeshuni↗
Converter-Interfaced CHP Plant for Improved Grid-Integration, Flexibility and Resiliency
GE Research and its partner GE Renewables have proposed the use of an interface converter solution to increase the penetration of small to medium-sized CHP (1MWe to 20MWe) into distribution grids and improve their flexibility and grid support capability. Indeed, the proposed interface converter solution thanks to presence of the grid-ready inverter, allows to streamline the compliance to grid codes requirements, reduce the interconnection delays and costs and ultimately one of the main barriers for CHP adoption by commercial and industrial facilities. An additional benefit provided by the interface converter is the use of the grid-ready inverter for reactive power which eliminates the need of sizing the generator for that capability. These two benefits highly favor the economic feasibility of converter-interfaced CHP. Five user cases, each in one of the leading U.S states for CHP potential reported by the DOE in its estimation of the U.S Technical Potential of CHP, were selected to compare the economic performances of converter-interfaced CHP as compared with directly-coupled. They include a college campus in California, a hospital in New York, a water reclamation plant in Texas, a hotel in Minnesota, and a large office building in Pennsylvania. Results showed that, the presence of the interface converter allows to increase the return on investment (ROI) by 0.5 to 2 percentage points in most of the cases (4 of 5). Indeed, the interface converter by shortening the interconnection process allows to accelerate revenues while reducing interconnection costs. Added to the reduced cost of the required generator these savings trade favorably the capital cost of the converter. The analysis also showed that the profitability of the converter-interfaced CHP is highly sensitive to the energy price, interconnection delay, and converter cost. However, it appears that if the interface converter can shorten the interconnection process by at least 6 months, adopting this solution will be more economically viable than directly-coupled configuration in almost all the +23,000 sites of the U.S Technical Potential CHP. The evaluation of the benefits of a converter-interfaced CHP also showed that it enables higher ROI when coupled with other distributed energy resources (DER) such as battery energy systems (BESS) or solar photovoltaic (PV). Indeed, in those scenario, the grid-ready inverter included in the interface converter eliminates the need of separate inverters if DC-coupling is used. On the technical performance, it has been verified that the presence of the interface converter allows to reduce by 70% to 80% the CHP short-circuit contribution to grid faults. This not only reduces the mechanical and thermal stresses exposed to the CHP electrical components but also increases the grid hosting capacity which ultimately enables higher penetrations CHP. Another key benefit of the interface converter validated with hardware-in-the-loop simulations and testing is its superior capability for reactive power support. Indeed, using a power hardware testbed with two +700kW inverters configured in back-to-back, a microgrid controller and actual facilities loads it was demonstrated that the presence of the interface converter can help maintain a power factor near ~1 or regulate the voltage to ~1.0pu at the point of common coupling. This benefit can be highly valuable if in the future, due to higher penetration of renewable distributed energy resources (DER), utilities start billing demand charge based on kVA instead of kW as currently. It was also validated that converter-interfaced CHP can dispatch heat and power commands and seamlessly switch between the two modes while consistently controlling the power factor or voltage at PCC. Indeed, the power hardware testing showed that grid-connected converter-interfaced CHP can follow either the power or heat demand while maintaining a unity power factor at converter output. This research proved that the adoption of an interface converter as the solution for interconnection of CHP system into the distribution grid can greatly improve the economic feasibility of small to medium-sized CHP as well as the plant power quality, flexibility and resiliency. Additionally, it allows increased penetrations of CHP into the distribution grid, extends their grid support capability, and facilitates the integration of BESS and PV DER by streamlining their collocation within the same facilities. This ultimately provides an opportunity for commercial and small industrial facilities in the U.S to accelerate their energy transition thanks to the high energy efficiency of CHP systems and its reliable, flexible, and resilient microgrid operation when interconnected with an interface converter.
24 POWER TRANSMISSION AND DISTRIBUTION↗
High Throughput In-Line Coating Metrology Development for Solid Oxide Fuel Cell Manufacturing
Coatings play key roles in solid oxide fuel cell (SOFC) stack durability. For example, diffusion barrier coatings on Cr-containing interconnect and balance of plant (BOP) components protect electrodes from Cr poisoning over the long operational lifetimes (>10,000 hours) of the fuel cell stack. Common defects in coatings, such as cracks, pinholes, and porosity, result in a failure to protect the electrodes, resulting in shorter operational lifetime and thus higher cost. It is very unlikely, even in the best coating process, that all these defects can be mitigated, hence identifying critical defects in parts, and removing defective parts from production before they can damage the stack, becomes paramount. Furthermore, these quality control techniques must be operational in the production/assembly line (in-line), i.e., high throughput and non-destructive, and cost effective. Redox Power Systems, LLC (Redox) together with the National Renewable Energy Laboratory (NREL) developed much needed high throughput, in-line metrology techniques for protective coatings. The overall goal of the project is to lower cost while increasing robustness, reliability, and endurance of SOFC stacks. To accomplish this, we had several objectives, including: to identify key coating and substrate defects that lead to coating failure through the use of detailed characterization methods (e.g., microscopy, XRD, EDS, electrochemistry); to assess capabilities of in-line metrology techniques, e.g., optical profilometry (Redox) and thermography (NREL), to probe these defects, or evidence thereof; demonstrate long-term performance of “defect-free” protective coatings, as identified by in-line metrology, in solid oxide fuel cell (SOFC) stack operation. In the first part of this project, the ability to identify key defects expected to lead to coating and SOFC degradation using in-line metrology tools were evaluated. Coated interconnect samples with controlled defect types and populations were tested under conditions similar to SOFC operation, followed by detailed post-test analysis to reveal the defects responsible for observed degradation. In the second part of the project, the optimal in-line metrology techniques and methodologies were used to map the defect distribution in full-size interconnects with critical defects intentionally allowed to exist in some cases. These interconnects underwent SOFC testing for extended periods (up to ~3,000 hours) followed by post-test analysis to evaluate the effectiveness of in-line metrology techniques in mitigating MCO coating related degradation. Key accomplishments in this project included the following: Demonstrated ASR of < 0.05 ohm-cm 2 at 650 °C for 1,000 hours with low defect (determined by in-line metrology) interconnect samples (average ASR=37 milliohms-cm 2 after over 1,000 hours). Demonstrated that low defect coatings on interconnects (as screened using in-line metrology) have low volatilization of chromium at ~650 °C for 1,000 hours as detected using Cr-getter material (< 5 at% increase above baseline); 1022 hour duration tests under humidified, elevated temperature (750 °C rather than 650 °C) compared a base case against different coating thicknesses. Demonstrated capability to identify initial key defects of interest with in-line metrology techniques using up to 8 cm by 10 cm having coatings with and without intentional defects of interest using thermal imaging and optical profilometry. Correlated key defects identified using metrology techniques with observed coating performance (e.g., ASR and Cr volatility). Conducted several 4 cm by 4 cm cell tests using MCO-interconnects that were pre-screened using some of the metrology techniques developed in the project (e.g., optical profilometry). An analysis of ASR measurements were able to show that defect-free coatings resulted in the anticipated performance in the cell tests.
01 COAL, LIGNITE, AND PEAT↗
Skylab observations of X-ray loops connecting separate active regions
One hundred loops interconnecting 94 separate active solar regions detectable in soft X-rays were identified during the Skylab mission. While close active regions are commonly interconnected with loops, the number of such interconnections decreases steeply for longer distances; the longest interconnecting loop observed in the Skylab data connected regions separated by 37 deg. Several arguments are presented which support the point of view that this is the actual limit of the size of magnetic interconnections between active regions. No sympathetic flares could be found in the interconnected regions. These results cast doubt on the hypothesis that accelerated particles can be guided in interconnecting loops from one active region to another over distances of 100 deg or more and eventually produce sympathetic flares in them.
Chase, R. C.↗
Pressurized bellows flat contact heat exchanger interface
Disclosed is an interdigitated plate-type heat exchanger interface. The interface includes a modular interconnect to thermally connect a pair or pairs of plate-type heat exchangers to a second single or multiple plate-type heat exchanger. The modular interconnect comprises a series of parallel, plate-type heat exchangers arranged in pairs to form a slot therebetween. The plate-type heat exchangers of the second heat exchanger insert into the slots of the modular interconnect. Bellows are provided between the pairs of fins of the modular interconnect so that when the bellows are pressurized, they drive the plate-type heat exchangers of the modular interconnect toward one another, thus closing upon the second heat exchanger plates. Each end of the bellows has a part thereof a thin, membrane diaphragm which readily conforms to the contours of the heat exchanger plates of the modular interconnect when the bellows is pressurized. This ensures an even distribution of pressure on the heat exchangers of the modular interconnect thus creating substantially planar contact between the two heat exchangers. The effect of the interface of the present invention is to provide a dry connection between two heat exchangers whereby the rate of heat transfer can be varied by varying the pressure within the bellows.
Voss, Fred E.↗
SpaceVPX Interoperability Assessment
The existing VMEbus (VersaModular Eurocard bus) International Trade Association (VITA)-78 industry standard, also known as SpaceVPX, is an avionics board- and chassis-level standard derived from the OpenVPX standard as defined in VITA-65. While VITA-65 defines backplane and board-level profiles from COTS vendors to ensure interoperability of products used in developing systems and subsystems, the VITA-78 standard defines SpaceVPX to incorporate fault tolerance features that are required by many spaceflight systems. However, VITA-78 allows so much flexibility that interoperability between modules cannot be assured. This assessment provides guidelines on the use of, and extensions to, the VITA-78 standard to enable avionics interoperability for future NASA missions. The assessment team was comprised of subject matter experts (SMEs) from Goddard Space Flight Center (GSFC), the Jet Propulsion Laboratory (JPL), Johnson Space Center (JSC), and Langley Research Center (LaRC). The team included valuable external consulting support from a SME who was a key participant in the development of the VITA-78 standard. The team had extensive collaboration with the NASA Space Technology Mission Directorate (STMD) High Performance Spaceflight Computing (HPSC) project, specifically in the development of SpaceVPX interconnect findings, observations, and NESC recommendations. To provide an understanding of the breadth of implementations that SpaceVPX must accommodate, multiple NASA use cases were analyzed to assess the requirements for SpaceVPX implementations across a wide range of NASA missions (Appendix C). Applications included crewed missions, science missions, and orbital and surface robotic systems. Product surveys were conducted to assess the level of industry support for SpaceVPX, applications, and the variations in their implementations (Appendix D). In-depth analysis was conducted in the areas of: (a) power management and distribution, (b) form factors and daughtercards, (c) interconnect, and (d) fault tolerance. Leveraging the use cases, product surveys, and SMEs from multiple NASA Centers, these areas were analyzed to determine the range of implementations permitted by the VITA-78 standard and potential interoperability issues. Applicable findings and NESC recommendations were provided for each area. During this assessment, there were multiple opportunities to engage with other agencies to learn about their interest in SpaceVPX, their strategies for implementing SpaceVPX-based systems, and their internal development efforts. These engagements also generated findings and NESC recommendations. Based on this assessment analysis, NESC recommendations were made regarding the feature set and module profiles to support NASA SpaceVPX implementations. This feature set includes restrictions on features in VITA-78, and extensions to the standard. Key recommendations in this area include the use of 10 Gigabit Ethernet and Peripheral Component Interconnect Express (PCIe) as high bandwidth interconnect on the backplane, the retention of SpaceWire interconnect for control functions, and support for 3U (unit) and 6U, form factors for NASA systems. Restrictions were proposed on the usage of user-defined signals to promote interoperability, and specific power managements and distribution schemes for 3U systems. Beyond the technical implementation of SpaceVPX, recommendations were made on areas that warrant further investigation. Primary among these is the recommendation for NASA to collaborate with other space-going agencies and industry to incorporate recommendations into a future ‘dot spec’ of VITA-78. This would ensure wide adoption and availability of the modules that comply with the specification. The assessment includes appendices with candidate module profiles that can be considered as a starting point for this activity, and example systems based on the recommendations. Follow-on studies are recommended for architectures beyond SpaceVPX to address potential enhancements including condensed set of interconnect, software required to implement protocol layers on the interconnect (and other features), alternative power architectures, and system-level testability.
SpaceVPX↗
System and method for obfuscation of electronic circuits
A computer-implemented method of generating randomized electrical interconnects for an electronic circuit comprises steps of receiving a netlist of nodes of electronic components to be connected, each connection between the nodes forming an electrical interconnect; determining a list of one or more path directions for each electrical interconnect; determining a plurality of path direction distances for each electrical interconnect; generating a plurality of segments for each electrical interconnect, each segment having one path direction and a length which are selected at random; calculating a sum of the lengths of all of the segments in each path direction each time a segment is generated for each electrical interconnect; removing one path direction from the list of path directions when a first condition is met; and stopping the generating a plurality of segments for each electrical interconnect when a second condition is met.
Trujillo, Joshua↗
System and method for obfuscation of electronic circuits
A computer-implemented method of generating randomized electrical interconnects for an electronic circuit comprises steps of receiving a netlist of nodes of electronic components to be connected, each connection between the nodes forming an electrical interconnect; determining a list of one or more path directions for each electrical interconnect; determining a plurality of path direction distances for each electrical interconnect; generating a plurality of segments for each electrical interconnect, each segment having one path direction and a length which are selected at random; calculating a sum of the lengths of all segments of the plurality of segments in each path direction each time a segment is generated for each electrical interconnect; removing one path direction from the list of path directions when a first condition is met; and stopping the generating a plurality of segments for each electrical interconnect when a second condition is met.
Trujillo, Joshua↗
Informative Background on the Interoperability Requirements in IEEE Std 1547-2018
The intent of this document is to support local authorities governing interconnection requirements in adopting the most current requirements for interconnecting distributed energy resources (DERs) to the electric distribution system, as specified in the Institute of Electrical and Electronics Engineers Standard for Interconnection and Interoperability of Distributed Energy Resources with Associated Electric Power Systems Interfaces (IEEE Std 1547-2018 ). To create interconnection rules that successfully address policy goals, market trends, and technical requirements, electric service regulators need to be well informed of DER integration considerations. Interconnection processes and technical issues often overlap; the two are not easily segregated, and they are often considered and evaluated concurrently within the context of interconnection rulemaking. Accordingly, this document addresses both the technical issues and related process considerations.
24 POWER TRANSMISSION AND DISTRIBUTION↗