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At least 577 records · Page 32
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Formal development of a clock synchronization circuit

This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.

Miner, Paul S.↗
NASA NTRS1998

Finite Ground Coplanar (FGC) Waveguide: It's Characteristics and Advantages for Use in RF and Wireless Communication Circuits

To solve many of the problems encountered when using conventional coplanar waveguide (CPW) with its semi-infinite ground planes, a new version of coplanar waveguide with electrically narrow ground planes has been developed. This new transmission line which we call Finite Ground Coplanar (FGC) waveguide has several advantages which make it a better transmission line for RF and wireless circuits. Since the ground planes are electrically narrow, spurious resonances created by the CPW ground planes and the metal carrier or package base are eliminated. In addition, lumped and distributed circuit elements may now be integrated into the ground strips in the same way as they traditionally have been integrated into the center conductor to realize novel circuit layouts that are smaller and have less parasitic reactance. Lastly, FGC is shown to have lower coupling between adjacent transmission lines than conventional CPW.

Ponchak, George E.↗
NASA NTRS1998

Finite Ground Coplanar (FGC) Waveguide: A Better Transmission Line for Microwave Circuits

A new version of coplanar waveguide (CPW) with electrically narrow ground strips 14 has been developed for microwave integrated circuits. This transmission line, referred to by Finite Ground Coplanar (FGC) waveguide, has several advantages over conventional coplanar waveguide. Since the ground strips are narrow, parasitic resonances that develop when the CPW is placed on a carrier or in a package are eliminated. In addition, the narrow ground strips permit the integration of lumped and distributed circuit elements in the ground strips as well as in the center strip to reduce the circuit size and improve its performance. Finally, the coupling between adjacent FGC transmission lines is lower than the coupling between CPW lines for the same spacing between the lines. All of these attributes of FGC are presented in this paper.

Ponchak, George E.↗
NASA NTRS2000

Optical Circuit Switched Protocol

The present invention is a system and method embodied in an optical circuit switched protocol for the transmission of data through a network. The optical circuit switched protocol is an all-optical circuit switched network and includes novel optical switching nodes for transmitting optical data packets within a network. Each optical switching node comprises a detector for receiving the header, header detection logic for translating the header into routing information and eliminating the header, and a controller for receiving the routing information and configuring an all optical path within the node. The all optical path located within the node is solely an optical path without having electronic storage of the data and without having optical delay of the data. Since electronic storage of the header is not necessary and the initial header is eliminated by the first detector of the first switching node. multiple identical headers are sent throughout the network so that subsequent switching nodes can receive and read the header for setting up an optical data path.

Monacos, Steve P.↗
NASA NTRS2001

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

Simons, Rainee N.↗
NASA NTRS1999

Silica Integrated Optical Circuits Based on Glass Photosensitivity

Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

Abushagur, Mustafa A. G.↗
NASA NTRS1986

Flexible Circuits

Adflex Solutions, Inc.'s flexible circuits may be molded to the shape of a chassis for bulk reduction. Particularly valuable when circuitry must be moved. They are produced by combining a plastic film, a metallic conductor and an adhesive. One adhesive, LARC-TPI, developed by the Langley Research Center, is a thermoplastic polyimide resin used to produce laminates by Rogers Corporation. It can be processed at a lower temperature, has good moisture resistance and excellent adherence. It is used to bond film to copper foil conductor materials in flexible circuits. The circuits have both aerospace and commercial applications.

Source record↗
NASA NTRS2003

Traveling-Wave Tube Cold-Test Circuit Optimization Using CST MICROWAVE STUDIO

The internal optimizer of CST MICROWAVE STUDIO (MWS) was used along with an application-specific Visual Basic for Applications (VBA) script to develop a method to optimize traveling-wave tube (TWT) cold-test circuit performance. The optimization procedure allows simultaneous optimization of circuit specifications including on-axis interaction impedance, bandwidth or geometric limitations. The application of Microwave Studio to TWT cold-test circuit optimization is described.

Chevalier, Christine T.↗
NASA NTRS2003

Electrical Devices and Circuits for Low Temperature Space Applications

The environmental temperature in many NASA missions, such as deep space probes and outer planetary exploration, is significantly below the range for which conventional commercial-off-the-shelf electronics is designed. Presently, spacecraft operating in the cold environment of such deep space missions carry a large number of radioisotope or other heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronic devices and circuits capable of operation at cryogenic temperatures will not only tolerate the harsh environment of deep space but also will reduce system size and weight by eliminating or reducing the heating units and their associate structures; thereby reducing system development cost as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior in the electrical and thermal properties of some semiconductor and dielectric materials at low temperatures. An on-going research and development program on low temperature electronics at the NASA Glenn Research Center focuses on the development of efficient electrical systems and circuits capable of surviving and exploiting the advantages of low temperature environments. An overview of the program will be presented in this paper. A description of the low temperature test facilities along with selected data obtained from in-house component testing will also be discussed. On-going research activities that are being performed in collaboration with various organizations will also be presented.

Patterson, R. L.↗
NASA NTRS2005

Single Event Transients in Linear Integrated Circuits

On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed to transients. In some cases, such events produced resets by falsely triggering circuits designed to protect against over- voltage or over-current. On at least three occasions, transients caused satellites to switch into "safe mode" in which most of the systems on board the satellites were powered down for an extended period. By the time the satellites were reconfigured and returned to full operational state, much scientific data had been lost. Fortunately, no permanent damage occurred in any of the systems and they were all successfully re-activated.

Buchner, Stephen↗
NASA NTRS2006

Lithium Circuit Test Section Design and Fabrication

The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper will discuss the overall system design and build and the component testing findings.

Godfroy, Thomas↗
NASA NTRS2006

Stainless Steel NaK Circuit Integration and Fill Submission

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

Garber, Anne E.↗
NASA NTRS2002

Complemenary body driving - a low voltage analog circuit technique for SOI

This paper describes several analog circuit primitives that utilize the body terminal as a signal port. A cascode current mirror that can operate with an input and output voltage of 200 mV; and a rail-to-rail, constant transconductance gain block capable of 1 V operation are presented. These circuits have been implemented in a standard 0.35~1 partially-depleted Silicon-on-Insulator (PDSOI) CMOS process and should find wide application in next-generation analog circuit designs.

neuro-prosthetic devices cortical signals↗
NASA NTRS2007

Assembly and Thermal Hydraulic Test of a Stainless Steel Sodium-Potassium Circuit

Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system was originally built for use with lithium, but due to a shift in focus, it was redesigned for use with a eutectic mixture of sodium potassium (NaK). Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This paper summarizes the first fill and checkout testing of the Stainless Steel NaK-Cooled Circuit (SNaKC).

Garber, A.↗
NASA NTRS2007

Evolutionary Technique for Automated Synthesis of Electronic Circuits

An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

Stoica, Adrian↗
NASA NTRS2007

Stainless Steel NaK-Cooled Circuit (SNaKC) Fabrication and Assembly

An actively pumped Stainless Steel NaK Circuit (SNaKC) has been designed and fabricated by the Early Flight Fission Test Facility (EFF-TF) team at NASA's Marshall Space Flight Center. This circuit uses the eutectic mixture of sodium and potassium (NaK) as the working fluid building upon the experience and accomplishments of the SNAP reactor program from the late 1960's The SNaKC enables valuable experience and liquid metal test capability to be gained toward the goal of designing and building an affordable surface power reactor. The basic circuit components include a simulated reactor core a NaK to gas heat exchanger, an electromagnetic (EM) liquid metal pump, a liquid metal flow meter, an expansion reservoir and a drain/fill reservoir To maintain an oxygen free environment in the presence of NaK, an argon system is utilized. A helium and nitrogen system are utilized for core, pump, and heat exchanger operation. An additional rest section is available to enable special component testing m an elevated temperature actively pumped liquid metal environment. This paper summarizes the physical build of the SNaKC the gas and pressurization systems, vacuum systems, as well as instrumentation and control methods.

Godfroy, Thomas J.↗
NASA NTRS2006

Functional Recovery of Analog Circuits at Extreme Temperatures

This paper describes a new reconfigurable analog array (RAA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithm-driven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environment. The experiments demonstrate circuit adaptation over a wide temperature range, from extremely low temperature of -180 C to high 120 C.

self-recovery↗
NASA NTRS1994

Conductance measurement circuit with wide dynamic range

A conductance measurement circuit to measure conductance of a solution under test with an output voltage proportional to conductance over a 5-decade range, i.e., 0.01 uS to 1000 uS or from 0.1 uS to 10,000 uS. An increase in conductance indicates growth, or multiplication, of the bacteria in the test solution. Two circuits are used each for an alternate half-cycle time periods of an alternate squarewave in order to cause alternate and opposite currents to be applied to the test solution. The output of one of the two circuits may be scaled for a different range optimum switching frequency dependent upon the solution conductance and to enable uninterrupted measurement over the complete 5-decade range. This circuitry provides two overlapping ranges of conductance which can be read simultaneously without discontinuity thereby eliminating range switching within the basic circuitry. A VCO is used to automatically change the operating frequency according to the particular value of the conductance being measured, and comparators indicate which range is valid and also facilitate computer-controlled data acquisition. A multiplexer may be used to monitor any number of solutions under test continuously.

Mount, Bruce E.↗