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566 records · Page 32
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Design optimization of MAPS-based detectors using a data-driven fast simulation approach

A parametric simulation tool for pixel sensors is presented. A realistic pixel response is simulated purely based on measurement input, without requiring detailed knowledge of the underlying manufacturing process. As such, it provides an efficient alternative to the use of Technology Computer-Aided Design simulations, which typically depend on proprietary process information. Due to its parametric approach, the package is fast and thus particularly useful for larger detector systems and high hit rate environments. This work presents measurements, simulation and its validation for the MALTA2 sensor. It is a small collection electrode monolithic active pixel sensor produced in the Tower 180 nm complementary metal-oxide-semiconductor imaging process. Modifications to the sensor’s periphery, mainly in the hit merger, are studied in order to optimize the performance for tracking and calorimetry. This optimization is of special interest as part of the MALTA3 sensor redesign in the 65 nm Tower Partners Semiconductor Co. process.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

Novel and effective surface passivation for high efficiency n- and p-type Silicon solar cell

The project objective was to develop a novel Si surface passivation method using chalcogens, sulfur (S) and/or selenium (Se), as passivating elements, to withstand industry-standard high temperature contacting and metallization schemes for p-type Si based passivated emitter and rear contact (p-PERC) solar cells. The back surface passivation of PERC cells has been improved drastically with the invention and successful application of an Al 2 O 3 passivation layer. However, the front n + diffused junction surface is still poorly passivated by the standard amorphous silicon nitride (SiNx) anti-reflection coating (ARC) layer. This project sought to address the passivation challenges of both front n+ emitter and undiffused p-Si back surface. Improved p-PERC solar cell performance with open circuit voltage (V OC ) > 680 mV and efficiency of 22% were targeted to validate superior defect passivation properties as compared to standard SiO 2 / Al 2 O 3 passivation. During this project, we systematically investigated process-structure-properties-performance relationships of this novel advanced defect passivation approach. The S/Se passivation was carried out by reacting industrial Czochralski (Cz) Si wafers in H 2 S and H 2 Se gases in a chemical vapor deposition (CVD) reactor at temperatures up to 700°C. After an exhaustive optimization of the process parameters (temperature, time, and gas concentration), we established an optimized process and demonstrated extremely low surface recombination velocities (SRVs) of 1.5 cm/s and 8 cm/s on n-type and p-type Si, respectively, by S-passivation. In-depth surface and interface characterization were performed using soft x-ray and photoelectron spectroscopies (XPS, UPS, XES), combined with capacitance-voltage-frequency (C-V-f) measurements, to decipher the surface chemical/electronic structure and interface defect state densities. These measurements provided critical understanding of the defect passivation mechanism and elucidated the presence of surface S-Si bonds, a reduction of surface dipoles, and low interface state densities (D it ) < 10 11 cm -2 ev -1 . We also found that the Se-passivation is inferior to the S-passivation (by at least one order of magnitude in SRV). Application of the optimized S-passivation to the n+ diffused emitter surface led to a low surface recombination current density, J0 ≈ 40 fA/cm 2 (~ 1/4 of the industry-standard SiNx-passivation), and high implied V OC (686 mV) in p-PERC solar cell structures. The S-passivation process also was found to improve the bulk quality of the p-type Si, better than the SiO 2 or Al 2 O 3 passivation processes. After successful demonstration of efficient passivation of Si surface defects by S, we extensively studied the air, thermal, and illumination stability of the passivation structure. S-passivation itself degrades in air due to competing reactions with moisture and oxygen to form oxides, which can be eliminated by a SiNx capping layer (also acting as a anti-reflective coating). After SiNx process optimization, we demonstrated illumination and thermally stable S-passivation with SRV < 5 cm/s and J 0 < 80 fA/cm 2 . These enhancements in Si passivation, incorporated into p-PERC cells, achieved an efficiency of 19.93% with V OC = 649 mV, using manufacturing metallization and contacting schemes. The low cell performance (cell V OC is much less than the implied V OC = 686 mV, anticipated from surface passivation) was identified due to degradation of S-passivation during the metal firing step (out-diffusion of S from the Si interface to the SiNx surface). The S-passivation of Si surfaces shows significant promise with excellent passivation quality, essential for high performance (high V OC , high efficiency) solar cells. Integration of this innovative defect passivation into devices, however, demands further development of the capping layer, low temperature (<700°C) metallization process, and/or engineering of advanced device structures. Surface passivation-dominated advanced Si solar cells, such as tunnel oxide passivated contacts and Si heterojunctions, are increasingly of interest due to their high-performance potential and will have a growing photovoltaic market share in the near future.

14 SOLAR ENERGY↗
DOE OSTI2022

Self-Aligned Selective Area Front Contacts on Poly -Si/SiO x Passivating Contact c -Si Solar Cells

We report both polarity poly-Si/SiO x passivating contacts in a front/back device configuration may represent the next solar cell architecture after tunnel oxide passivating contacts (TOPCon) cells, but high parasitic absorption in the front poly -Si layer often limits its performance. This work explores a wet etching technique to remove the front poly -Si in the nonmetallized regions using self-aligned metal grids as an etch mask. We systematically examine various dielectric layers (SiN x ,Al 2 O 3 , and stacks thereof) to study the repassivation of the etched n + surface, and find that an SiN x /Al 2 O 3 passivation stack can effectively repassivate the etched surface, which we attribute to field-effect passivation from the positive fixed charge from the SiN x layer, and excellent chemical passivation property from Al 2 O 3 in the form of atomic H. We demonstrate a front/back poly-Si/SiO x passivating contact device, with an open-circuit voltage (V oc ) of 690 mV, short-circuit current density (J sc ) of 39.8 mA/cm 2 , fill factor of 78%, and power conversion efficiency of 21.4%. Furthermore, simulations using SunSolve and Quokka 3 show good agreement with both the optical and electrical properties of the experimental device. The power loss analysis reveals improvements in the optical loss from the back Ti adhesion and front SiN x layers would lead to a 23.5% device. Lastly, a techno-economic model compares the production cost of this improved cell with the current TOPCon cells. Our results highlight that further cost reductions in single-sided doped poly -Si layers are needed to compete with mainstream passivated emitter and rear cell, and TOPCon technologies.

14 SOLAR ENERGY↗
DOE OSTI2025

Electric Drive Technologies Consortium (EDTC)/ Cost competitive, high-Performance, highly Reliable (CPR) Power Devices on 4H-SiC (Final Report)

4H-Silicon carbide (4H-SiC) is a wide bandgap semiconductor that offers superior material properties over silicon, including higher critical electric field, thermal conductivity, and electron saturation velocity. These advantages make 4H-SiC highly attractive for high-voltage, high-efficiency power electronics. However, realizing the full potential of SiC requires device technologies that are not only high-performing but also manufacturable and reliable under real-world operating conditions. This report summarizes the outcomes of a five-year R&D effort funded by the U.S. Department of Energy (DOE) under the Electric Drive Technologies Consortium (EDTC), focused on developing cost-competitive, high-performance, and highly reliable (CPR) power devices on 4H-SiC substrates. The program targeted scalable and manufacturable 1.2 kV-class SiC MOSFETs optimized for next-generation electric vehicles, renewable energy systems, and industrial power conversion. The project delivered transformative advancements in SiC power device performance and ruggedness. Particularly, Specific on-resistance (R on,sp ) was reduced by up to 37%, from ~4.0 m$\Omega \cdot$cm 2 in earlier designs to an industry-leading 2.40 m$\Omega \cdot$cm 2 , driven by optimized doping, refined JFET widths, and layout engineering. Breakdown voltages (BV) exceeded 1600 V, marking improvement over legacy baselines, and demonstrating the robustness of newly implemented junction profiles and edge terminations. Short-circuit withstand time (SCWT) saw a remarkable 4$\times$ increase, from ~2 $\mu$s to over 8 $\mu$s, achieved through the successful deployment of deep P-well structures (~1.8–2.0 $\mu$m) via channeling implantation. This innovative process breakthrough enabled precise junction formation without MeV-class implantation tools, reduced leakage under high field stress, and allowed even the shortest-channel devices (down to 0.3 $\mu$m) to achieve both high BV and excellent ruggedness—breaking the traditional trade-off between conduction efficiency and blocking capability. Several novel architectures pushed the performance envelope further. JBSFETs—featuring embedded Schottky portions—eliminated bipolar degradation and drastically reduced third-quadrant leakage, while Ladder MOSFETs introduced a clever orthogonal conduction path that achieved a 15.4% reduction in R on,sp over standard linear designs. Switching performance reached new benchmarks: short-channel devices showed a 31% reduction in total switching energy compared to 0.5 $\mu$m counterparts, while maintaining manageable gate drive requirements. Layout-optimized structures not only improved transconductance but also accelerated switching transitions, pointing to real-world benefits in converter-level efficiency. The devices also passed rigorous reliability validation. Stress-tested across TDDB, HTGB, HTRB, HVP, and burn-in, the devices screened under 30 V/10 hr and 43 V/1 s protocols consistently exhibited tighter lifetime distributions and long-term oxide robustness. These screening techniques proved effective in identifying latent defects and ensuring deployment-grade reliability. Meanwhile, advanced 3D TCAD simulations revealed and resolved electric field hotspots—particularly in HEXFET corners—where fields exceeding 4.8 MV/cm were mitigated through geometry-aware layout corrections. Overall, the results of this project demonstrate a manufacturable and scalable SiC power device platform that addresses key DOE performance targets for efficient, robust, and reliable 1.2kV 4H-SiC Power Devices. The developed technologies represent a meaningful step forward in the commercial readiness of high-voltage SiC solutions and provide a strong foundation for continued advancement in wide bandgap power electronics.

42 ENGINEERING↗
DOE OSTI2024

Silicon implantation and annealing in β -Ga 2 O 3 : Role of ambient, temperature, and time

Optimizing thermal anneals of Si-implanted β-Ga 2 O 3 is critical for low resistance contacts and selective area doping. Here we report the impact of annealing ambient, temperature, and time on the activation of room temperature ion-implanted Si in β-Ga 2 O 3 at concentrations from 5 × 10 18 to 1 × 10 20 cm −3 , demonstrating full activation (>80% activation, mobilities >70 cm 2 /V s) with contact resistances below 0.29 Ω mm. Homoepitaxial β-Ga 2 O 3 films, grown by plasma-assisted molecular beam epitaxy on Fe-doped (010) substrates, were implanted at multiple energies to yield 100 nm box profiles of 5 × 10 18 , 5 × 10 19, and 1 × 10 20 cm −3 . Anneals were performed in an ultra-high vacuum-compatible quartz furnace at 1 bar with well-controlled gas compositions. To maintain β-Ga 2 O 3 stability, p O2 must be greater than 10 −9 bar. Anneals up to p O2 = 1 bar achieve full activation at 5 × 10 18 cm −3, while 5 × 10 19 cm −3 must be annealed with p O2 ≤ 10 −4 bar, and 1 × 10 20 cm −3 requires p O2 < 10 −6 bar. Water vapor prevents activation and must be maintained below 10 −8 bar. Activation is achieved for anneal temperatures as low as 850 °C with mobility increasing with anneal temperatures up to 1050 °C, though Si diffusion has been reported above 950 °C. At 950 °C, activation is maximized between 5 and 20 min with longer times resulting in decreased carrier activation (over-annealing). This over-annealing is significant for concentrations above 5 × 10 19 cm −3 and occurs rapidly at 1 × 10 20 cm −3 . Rutherford backscattering spectrometry (channeling) suggests that damage recovery is seeded from remnant aligned β-Ga 2 O 3 that remains after implantation; this conclusion is also supported by scanning transmission electron microscopy showing retention of the β-phase with inclusions that resemble the γ-phase.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2026

Epitaxy of Beta-Ga2O3 on Highly-Offcut (Greater than 10 Degrees) Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction.1 These films show step-flow growth from (-201) step-edges and high electron mobility. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (4.8 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe 100% reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Fast Growth of Ga2O3 on Highly Offcut (100)-Oriented Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. More importantly, the impact ionization coefficients along the [100] direction are low, leading to the highest possible critical fields. This is advantageous compared to the current state of the art, (001), due to reduced surface defects and increased possible breakdown voltage. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption, and on-axis (100) growth easily forms twin domains. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction. These films show step-flow growth from (20-1) step-edges and high electron mobility due to suppressed twins. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (>5 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3 and critical breakdown field in Schottky barrier diodes comparable with state-of-the-art (001) Ga2O3 without edge termination.

36 MATERIALS SCIENCE↗