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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 577 records · Page 32
All sourcesNASA NTRSDOE OSTI
DOE OSTI2019

Device and method for the location and identification of a radiation source

A handheld device for the location and identification of a radiation source, including: a radiation transparent housing; a radiation locator device disposed within the radiation transparent housing operable for determining the location of the radiation source, wherein the radiation locator device includes a plurality of gamma detection crystals arranged in a geometric pattern and separated by a gamma shielding material, a plurality of detectors coupled to the plurality of gamma detection crystals, and a processor module coupled to the plurality of detectors; one or more of a neutron detection crystal and a gamma spectroscopy crystal disposed within the radiation transparent housing adjacent to the radiation locator device; and one or more detectors coupled to the one or more of the neutron detection crystal and the gamma spectroscopy crystal and the processor module; wherein the one or more of the neutron detection crystal and the gamma spectroscopy crystal, the one or more detectors, and the processor module are collectively operable for identifying the radiation source.

Vencelj, Matjaz↗
DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗
DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗
DOE OSTI2016

System, method, and computer program product for scheduling tasks associated with continuation thread blocks

A system, method, and computer program product for scheduling tasks associated with continuation thread blocks. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor.

Ricketts, Scott↗
DOE OSTI2019

System and method for adaptive range 3D scanning

A scanner system is configured for acquiring three dimensional image information of an object. The scanner includes a projector, a camera, a graphics processing device, and a processor. The projector projects one of several pre-defined patterns upon the object. The camera captures an image from the object, which is received by the processor. The processor approximates mutual information from the object and the pattern using the graphics processing device, and selects a second pattern for projecting on the object.

Rosman, Guy↗
DOE OSTI2019

Real time feedback-based optimization of distributed energy resources

An example device includes a processor configured to receive a plurality of voltage values corresponding to voltage nodes in a first portion of a power system and determine, for each voltage node, a respective value of first and second voltage-constraint coefficients. The processor is also configured to receive a power value corresponding to a connection point of the first portion of the power system with a second portion of the power system and determine for the connection point, a respective value of first and second power-constraint coefficients. The processor is also configured to cause at least one energy resource connected to the first portion of the power system to modify an output power of the at least one energy resource based on the value of the first and second voltage-constraint coefficients for each voltage node and the value of the first and second power-constraint coefficients.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Dynamically adapting mechanism for translation lookaside buffer shootdowns

An operating system (OS) of a processing system having a plurality of processor cores determines a cost associated with different mechanisms for performing a translation lookaside buffer (TLB) shootdown in response to, for example, a virtual address being remapped to a new physical address, and selects a TLB shootdown mechanism to purge outdated or invalid address translations from the TLB based on the determined cost. In some embodiments, the OS selects an inter-processor interrupt (IPI) as the TLB shootdown mechanism if the cost associated with sending an IPI is less than a threshold cost. In some embodiments, the OS compares the cost of using an IPI as the TLB shootdown mechanism versus the cost of sending a hardware broadcast to all processor cores of the processing system as the shootdown mechanism and selects the shootdown mechanism having the lower cost.

42 ENGINEERING↗
DOE OSTI2020

Constructing a conforming Voronoi mesh for an arbitrarily-shaped enclosed geometric domain

A computing system is described herein, where the computing system includes a processor and memory storing instructions that, when executed by the processor, cause the processor to perform the following acts: 1) receiving a computer-implemented definition of an enclosed geometric domain, wherein the geometric domain is two-dimensional; 2) determining locations of seeds for the enclosed geometric domain; 3) decomposing the enclosed geometric domain into a conforming Voronoi mesh based on the locations of the seeds, wherein the conforming Voronoi mesh comprises Voronoi cells, and further wherein the conforming Voronoi mesh is bounded by the enclosed domain; and 4) performing a numerical simulation to generate simulation results, wherein the numerical simulation is based on at least one Voronoi cell in the Voronoi cells of the conforming Voronoi mesh.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Constructing a conforming voronoi mesh for an arbitrarily-shaped enclosed geometric domain

A computing system is described herein, where the computing system includes a processor and memory storing instructions that, when executed by the processor, cause the processor to perform the following acts: 1) receiving a computer-implemented definition of an enclosed geometric domain, wherein the geometric domain is three-dimensional; 2) determining locations of seeds for the enclosed geometric domain; 3) decomposing the enclosed geometric domain into a conforming Voronoi mesh based on the locations of the seeds, wherein the conforming Voronoi mesh comprises Voronoi cells, and further wherein the conforming Voronoi mesh is bounded by the enclosed domain; and 4) performing a numerical simulation to generate simulation results, wherein the numerical simulation is based on at least one Voronoi cell in the Voronoi cells of the conforming Voronoi mesh.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Device and method for cache utilization aware data compression

A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.

Das, Shomit N.↗
DOE OSTI2021

Real time feedback-based optimization of distributed energy resources

An example device includes a processor configured to receive a plurality of voltage values representing respective voltage magnitudes at voltage nodes in a first portion of a power system and determine, for each voltage node, a respective value of first and second voltage-constraint coefficients. The processor is also configured to receive a power value corresponding to a connection point of the first portion of the power system with a second portion of the power system and determine for the connection point, a respective value of first and second power-constraint coefficients. The processor is also configured to cause at least one energy resource connected to the first portion of the power system to modify an output power of the at least one energy resource based on the value of the first and second voltage-constraint coefficients for each voltage node and the value of the first and second power-constraint coefficients.

Dall'Anese, Emiliano↗
DOE OSTI2021

Hardware accelerated dynamic work creation on a graphics processing unit

A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Gutierrez, Anthony↗
DOE OSTI2021

Bringing OpenCL to Commodity RISC-V CPUs

The importance of open-source hardware has been increasing in recent years with the introduction of the RISC-V Open ISA. This has also accelerated the push for support of the open-source software stack from compiler tools to full-blown operating systems. Parallel computing with today’s Application Programming Interfaces such as OpenCL has proven to be effective at leveraging the parallelism in commodity multi-core processors and programmable parallel accelerators. However, to the best of our knowledge, there is currently no publicly available implementation of OpenCL targeting commodity RISC-V processors that is accessible to the open-source community. Besides opening RISC-V to the existing rich variety of scientific parallel applications, OpenCL also provides access to a unique genre of benchmarks useful in computer architecture research. In this work, we extended an Open-source implementation of OpenCL to target RISC-V CPUs. Our work not only cover commodity multi-core RISC-V processors, but also plethora of low- profile embedded RISC-V CPUs that often do not support atomic instructions or multi-threading.

Tine, Blaise↗
DOE OSTI2021

Ultra-compact system for characterization of physical, chemical and ignition properties of fuels

The present disclosure relates to a miniaturized fuel laboratory system that makes use of a housing, a processor housed within the housing, and a fuel inlet port supported from the housing for receiving a quantity of fuel to be used as a fuel test sample. The system may also have at least one fuel sensor housed in the housing in communication with the fuel inlet port for receiving the fuel test sample and carrying out combustion thereof. An electronic component may be housed in the housing, which enables communication with an external remote subsystem. A database may be incorporated which contains at least one of stored fuel characteristics or stored fuel analysis models, accessible by the processor. The processor may use fuel oxidation information generated by the fuel sensor, and at least one of the stored fuel characteristics or stored combustion models, to determine at least one fuel characteristic of the fuel test sample.

McNenly, Matthew J.↗
DOE OSTI2021

Low-observability matrix completion

An example device includes at least one processor configured to receive electrical parameter values corresponding to at least one first location within a power network. The at least one processor is further configured to determine, using matrix completion and based on the at least one electrical parameter value, an estimated value of at least one unknown electrical parameter. The at least one unknown electrical parameter corresponds to a second location within the power network. The at least one processor is also configured to cause at least one device within the power network to modify operation based on the estimated value of the at least one unknown electrical parameter.

Bernstein, Andrey↗
DOE OSTI2021

Vector send operation for message-based communication

Methods and systems for conducting vector send operations are provided. The processor of a sender node receives a request to perform a collective send operation (e.g., MPI_Broadcast) from a user application, requesting a copy of data in one or more send buffers by sent to each of a plurality of destinations in a destination vector. The processor invokes a vector send operation from a software communications library, placing a remote enqueue atomic send command for each destination node of the destination vector in an entry of a transmit data mover (XDM) command queue in a single call. The processor executes all of the commands in the XDM command queue and writes the data in the one or more send buffers into each receive queue of each destination identified in the destination vector.

Byrne, John L.↗
DOE OSTI2022

Control flow guided lock address prefetch and filtering

A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

Mashimo, Susumu↗
DOE OSTI2022

Multi-frequency electrical impedance tomography

Apparatus includes a plurality of geological subsurface electrical line sensors spaced apart from each other proximate a predetermined geological subsurface region of interest, with at least one of the electrical line sensors situated as a line source to produce a multi-frequency electrical impedance tomography source signal, and with at least one of the electrical line sensors situated as a line detector to receive the multi-frequency electrical impedance tomography response signal associated with the source signal that propagates through the predetermined geological subsurface region of interest, and a controller including a processor and a memory configured with instructions that, when executed by the processor, cause the processor to determine an electrical mapping over the predetermined geological subsurface region of interest based on the multi-frequency electrical impedance tomography source signal, response signal, and the spatial positions of the geological subsurface electrical line sensors.

Karra, Satish↗