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A hardware unit has been designed that reduces the cost, in terms of performance and power consumption, for implementing N-modular redundancy (NMR) in a multiprocessor device. The innovation monitors transactions to memory, and calculates a form of sumcheck on-the-fly, thereby relieving the processors of calculating the sumcheck in software
Transducing materials are being used in many aspects of our daily life serving as actuators, sensors, displays, communications and other components of commercial mechanisms. At JPL, such materials are being used to enable novel space and terrestrial applications. This effort involves mostly the use of piezoelectric, electroactive polymers (EAP), and shape memory alloys (SMA). The piezoelectric based devices and mechanisms that were developed include ultrasonic motors, piezopump, ultrasonic/sonic drilledcorer (USDC), and ferrosource. Further, the electroactive polymers were used to demonstrate a gripper, wiper, lifter and haptic interfaces. The research and develop tasks consists of analytical modeling, experimental corroboration, material characterization as well as devices and mechanisms design, construction and demonstration.
Chalcogenide phase change materials (PCMs) are a unique class of compounds whose switchable optical and electronic properties have fueled an explosion of emerging applications in microelectronics and microphotonics. Key to any application is the ability of PCMs to reliably switch between crystalline and amorphous states over a large number of cycles. While this issue has been extensively studied in the case of microelectronic memories, current PCM-based optical devices suffer from much inferior endurance. To understand the failure mechanisms limiting endurance of PCMs specifically in microphotonic devices, we have developed an on-chip resistive micro-heater platform and an automatic multi-modal characterization system to analyze cycling performance of optical PCMs. Reversible switching of large-area PCM devices over 50,000 cycles was demonstrated.
Techniques are disclosed for training machine learning systems. An input device receives training data comprising pairs of training inputs and training labels. A generative memory assigns training inputs to each archetype task of a plurality of archetype tasks, each archetype task representative of a cluster of related tasks within a task space and assigns a skill to each archetype task. The generative memory generates, from each archetype task, auxiliary data comprising pairs of auxiliary inputs and auxiliary labels. A machine learning system trains a machine learning model to apply a skill assigned to an archetype task to training and auxiliary inputs assigned to the archetype task to obtain output labels corresponding to the training and auxiliary labels associated with the training and auxiliary inputs assigned to the archetype task to enable scalable learning to obtain labels for new tasks for which the machine learning model has not previously been trained.
A magneto-electronic device may include: a spin-orbit torque (SOT) generator layer; a magnetic memory layer; and/or sensing electrodes configured to measure a Hall effect of the magnetic memory layer. The SOT generator layer may include topological insulator material, and the magnetic memory layer may include ferromagnetic material with perpendicular magnetic anisotropy. A magneto-electronic device may include: a spin-orbit torque (SOT) generator layer; a first magnetic memory layer on the SOT generator layer; an insulating layer on the first magnetic memory layer; and/or a second magnetic memory layer on the insulating layer. The SOT generator layer may include topological insulator material. The first magnetic memory layer and the second magnetic memory layer may include ferromagnetic material with either perpendicular magnetic anisotropy or in-plane magnetic anisotropy.
We describe the replacement of MPI with UPC++ in an existing Kokkos code that simulates heat conduction within a rectangular 3D object, as well as an analysis of the new code’s performance on CUDA accelerators. The key challenges were packing the halos in Kokkos data structures in a way that allowed for UPC++ remote memory access, and streamlining synchronization costs. Additional UPC++ abstractions used included global pointers, distributed objects, remote procedure calls, and futures. We also make use of the device allocator concept to facilitate data management in memory with unique properties, such as GPUs. Our results demonstrate that despite the algorithm’s good semantic match to message passing abstractions, straightforward modifications to use UPC++ communication deliver vastly improved performance and scalability in the common case. We find the one-sided UPC++ version written in a natural way exhibits good performance, whereas the message-passing version written in a straightforward way exhibits performance anomalies. We argue this represents a productivity benefit for one-sided communication models.
A liquid-crystal TV spatial light modulator (LCTV SLM) input device and LCTV nonlinear thresholding element are presently used to accomplish an all-optical implementation of an inner-product neural associative memory. This architecture represents an alternative to the vector-matrix multiplication method of the Hopfield model, which is most often employed by neural network associative memory models. LCTV SLM experimental results are presented and discussed.
An apparatus for characterizing the magnetic field of a device under test is discussed. The apparatus is comprised of five separate devices: (1) a device for nullifying the ambient magnetic fields in a test environment area with a constant applied magnetic field; (2) a device for rotating the device under test in the test environment area; (3) a device for sensing the magnetic field (to obtain a profile of the magnetic field) at a sensor location which is along the circumference of rotation; (4) a memory for storing the profiles; and (5) a processor coupled to the memory for characterizing the magnetic field of the device from the magnetic field profiles thus obtained.
Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have emerged as promising non-volatile memory elements for microelectronics, compatible with back end of line (BEOL) complementary–metal–oxide semiconductor fabrication. This study investigates asymmetric electrode TaN/HZO/Ta devices with a 6 nm thick HZO layer as FTJs for multistate resistive memory applications. The individual FTJs exhibit a resistance ratio exceeding 10× when utilized as a binary state device, with pulsing between −1.7 and +1.4 V to set the high resistance state (HRS) and low resistance state (LRS), respectively. Following with reduced write voltage pulses allows the ferroelectric device to operate with a selection of over 32 distinct resistance states (2 5 bits) between the LRS and HRS. This work then explores the stability of the resistance states during write/read pulse cycling, along with the stability of the state after multiple read pulses. Accessing the multibit state shows stability within 50 reads with the binary state remaining stable for more than 4000 reads pulses. With their multistate tunability and versatility, FTJs hold promise as BEOL memory elements for compute-in-memory (CiM) arrays, binary digital memory, or weighted vector matrix multiplication applications with low power consumption during computations.
By integrating sensing, memory and processing functionalities, biological nervous systems are energy and area efficient. Emulating such capabilities in artificial systems is, however, challenging and is limited by the device heterogeneity of sensing and processing cores. Here we report an organic electrochemical transistor capable of sensing, memory and processing. The device has a vertical traverse architecture and a crystalline–amorphous channel that can be selectively doped by ions to enable two reconfigurable modes: a volatile receptor and a non-volatile synapse. As a volatile receptor, the device is capable of multi-modal sensing and is responsive to stimuli such as ions and light. As a non-volatile synapse, it is capable of 10-bit analogue states, low switching stochasticity and good state retention. We also show that the homogeneous integration of the devices could provide functions such as conditioned reflexes and could be used for real-time cardiac disease diagnoses via reservoir computing.
This paper discusses single-event upset in memories and microprocessors, along with the mechanisms that cause SEU effects.
A releasable fastening apparatus is presented. The device includes a connecting member and a housing. The housing supports a gripping mechanism that is adapted to engage the connecting member. A triggering member is movable within the housing between a first position in which it constrains the gripping mechanism in locked engagement with the connecting member, and a second position in which the gripping mechanism is disengaged from the connecting member. A shaped memory alloy actuator is employed for translating the triggering member from its first to its second position. The actuator is designed to expand longitudinally when transitioned from a martensitic to an austenitic state.
Electrical resistance of new solid-state device altered repeatedly by suitable control signals, yet remains at steady value when control signal removed. Resistance set at low value ("on" state), high value ("off" state), or at any convenient intermediate value and left there until new value desired. Circuits of this type particularly useful in nonvolatile, associative electronic memories based on models of neural networks. Such programmable analog memory resistors ideally suited as synaptic interconnects in "self-learning" neural nets. Operation of device depends on electrochromic property of WO3, which when pure is insulator. Potential uses include nonvolatile, erasable, electronically programmable read-only memories.
Reconfigurable devices offer the ability to program electronic circuits on demand. Here, in this work, we demonstrated on-demand creation of artificial neurons, synapses, and memory capacitors in post-fabricated perovskite NdNiO 3 devices that can be simply reconfigured for a specific purpose by single-shot electric pulses. The sensitivity of electronic properties of perovskite nickelates to the local distribution of hydrogen ions enabled these results. With experimental data from our memory capacitors, simulation results of a reservoir computing framework showed excellent performance for tasks such as digit recognition and classification of electrocardiogram heartbeat activity. Using our reconfigurable artificial neurons and synapses, simulated dynamic networks outperformed static networks for incremental learning scenarios. The ability to fashion the building blocks of brain-inspired computers on demand opens up new directions in adaptive networks.
A device and method for detecting presence of a wireless communication device having an antenna with intrinsic characteristics includes a transmitter, a receiver, a memory element, and a processing element. The transmitter may send a first signal to the antenna of the wireless communication device. The receiver may receive a second signal from the antenna of the wireless communication device, the second signal being a first portion of the first signal that is reflected by the antenna based on intrinsic characteristics of the antenna. The memory element may store intrinsic characteristic information for the antenna. The processing element may determine presence of the wireless communication device by analyzing the second signal against the intrinsic characteristic information stored in the memory element.
Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have attracted interest as non-volatile memory for microelectronics due to ease of integration into back-end-of-line (BEOL) complementary metal oxide semiconductor fabrication. This work examines asymmetric electrode NbN/HZO/Nb devices with 7 nm thick HZO as FTJs in a memory structure, with an output resistance that can be controlled by read and write voltages. The individual FTJs are measured to have a tunneling electroresistance of 10 during the read state without significant filament conduction formation and reasonable ferroelectric performance. Endurance and remanent polarizations of up to 10 5 cycles and 20 μC/cm 2 , respectively, are measured and are shown to be dependent on the cycling voltage. Electrical measurements demonstrate how magnitude of the write pulse can modulate the high state resistance and the read pulse influences both resistance values as well as separation of resistance states. Then, by using two opposite switching FTJ devices in series, a programmable nonvolatile resistor divider is demonstrated. Measurements of these two FTJ unit memory cells show wide applicability to a BEOL microfabrication process for a re-readable, rewritable, and nonvolatile memory cell.
A design concept of phase-separated amorphous nanocomposite thin films is presented that realizes interfacial resistive switching (RS) in hafnium-oxide-based devices. The films are formed by incorporating an average of 7% Ba into hafnium oxide during pulsed laser deposition at temperatures ≤400°C. The added Ba prevents the films from crystallizing and leads to ~20-nm-thin films consisting of an amorphous HfO x host matrix interspersed with ~2-nm-wide, ~5-to-10-nm-pitch Ba-rich amorphous nanocolumns penetrating approximately two-thirds through the films. This restricts the RS to an interfacial Schottky-like energy barrier whose magnitude is tuned by ionic migration under an applied electric field. Resulting devices achieve stable cycle-to-cycle, device-to-device, and sample-to-sample reproducibility with a measured switching endurance of ≥10 4 cycles for a memory window ≥10 at switching voltages of ±2 V. Each device can be set to multiple intermediate resistance states, which enables synaptic spike-timing–dependent plasticity. The presented concept unlocks additional design variables for RS devices.
The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 - 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.