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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Under an SBIR contract with Glenn, SiCOM, Inc. has developed circuit cards for improved wireless communications. The high-speed wireless digital modem is useful for satellite to earth communication links. Commerical applications include HDTV broadcasts, digital satellite news gathering, Ethernet links and Local Multipoint Distribution Service (LMDS). The cards are programmable and allow customers to choose modulation frequencies to best serve their needs.
Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.
Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.
This paper reports recent single-event latchup results for a variety of microelectronic devices that include an ADC, OpAmp, EEPROM, CPLD, PWM, transceiver, voltage regulator, digital signal processor, step-down converter, buck controller and supervisory circuits. The data were collected to evaluate these devices for possible use in NASA ISS payloads.
Novel GaAs 8-bit slice enables quick and efficient implementation of variety of fast GaAs digital systems ranging from central processing units of computers to special-purpose processors for communications and signal-processing applications. With GaAs 8-bit slice, designers quickly configure and test hearts of many digital systems that demand fast complex arithmetic, fast and sufficient register storage, efficient multiplexing and routing of data words, and ease of control.
The idea of introducing redundancy to improve the reliability of digital systems originates from papers published in the 1950's. Since then, redundancy has been recognized as a realistic means for constructing reliable systems. A method using redundancy to reconfigure the Sequency Invariant State Machine (SISM) to achieve fault tolerance is introduced. This new architecture is most useful in space applications, where recovery rather than replacement of faulty modules is the only means of maintenance.
An all-digital technique to convert pulse code modulated (PCM) signals into adaptive delta modulation (ADM) format is presented. The converter developed is shown to be independent of the statistical parameters of the encoded signal and can be constructed with only standard digital hardware. The structure of the converter is simple enough to be fabricated on a large scale integrated circuit where the advantages of reliability and cost can be optimized. A concise evaluation of this PCM to ADM translation technique is presented and several converters are simulated on a digital computer. A family of performance curves is given which displays the signal-to-noise ratio for sinusoidal test signals subjected to the conversion process, as a function of input signal power for several ratios of ADM rate to Nyquist rate.
A digital speed control that can be combined with a proportional analog controller is described. The stability and transient response of the analog controller were retained and combined with the long-term accuracy of a crystal-controlled integral controller. A relatively simple circuit was developed by using phase-locked-loop techniques and total error storage. The integral digital controller will maintain speed control accuracy equal to that of the crystal reference oscillator.
A laser velocimeter signal processor for measuring the signal frequency within a signal burst. The input signal is converted to digital by an ADC 16 and then shifted into shift registers 30 and 31. An automatic gain circuit 15 controls the gain of the input signal. A signal integration circuit 32 determines when a signal burst has been captured by the shift registers and then transfers the contents of the registers to data latches 33 and 34. The data in data latches 33 and 34 is processed by digital bandpass filters 57-63, square law detectors 64-70, burst counters 71-77 and signal processor 78 to determine the frequency of the signal within the captured signal burst.
System feasibility testing of analog voltage to duty cycle generator, and production process for thin film tantalum resistors
Digital computer program requirements to process Apollo spacecraft electrical data for sneak circuit analysis
Mathematical model of proposed wind-tunnel facility represents wind-tunnel circuit and associated equipment in terms of lumped-parameter components. Requires less computational effort and computing time than full three-dimensional aerodynamic computer analysis of system with many volume elements. Approximates distributed nature of wind tunnel well enough to simulate steady-state and transient behavior for analysis of proposed control subsystems and for training of operators. Lumped-parameter circuit model represents wind tunnel and associated equipment. Implemented on analog or digital computers to simulate wind-tunnel performance without risk to operators or equipment.
A knowledge-based expert system is described that provides an approach to solve a problem requiring an expert with considerable domain expertise and facts about available digital hardware building blocks. To design digital hardware systems from their high level VHDL (Very High Speed Integrated Circuit Hardware Description Language) representation to their finished form, a special data representation is required. This data representation as well as the functioning of the overall system is described.
Improved correlating subsystem of pseudorandom-code ranging system made possible by advent of fast, custom-made, very-large-scale integrated circuits. Performs far fewer arithmetical operations, contains much less specialized analog and digital circuitry, and used with large number of different codes.
Various papers on fiber optic and laser sensors are presented. Individual topics addressed include: fiber optic photoelastic pressure sensor for high-temperature gases, fiber optic gyroscope using an eight-component LiNbO3 integrated optic circuit, design and performance of a fiber optic gyroscope using integrated optics, digital angular position sensor using wavelength division multiplexing, simple repeatable fiber optic intensity sensor for temperature measurement, compensation for effects of ambient temperature on rare-earth-doped fiber optic thermometer.
This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.
This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.
A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.