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At least 559 records · Page 31

Evaluation of structural integrity using integrated testing and analysis

An integrated approach to dynamic testing and mathematical model analysis is described. The overall approach addresses four key tasks, namely, pretest planning and analysis, test data acquisition, data reduction and analysis, and test/analysis correlation and mathematical model updates. Several key software programs are employed to accomplish this task. They are a leading finite element code, a sophisticated data analysis processor and a graphical pre- and post-processor along with an advanced interface utility. Several practical structures are used to illustrate tools and concepts employed in the integrated test analysis process.

Coppolino, Robert N.↗

Embedded Data Processor and Portable Computer Technology testbeds

Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

Alena, Richard↗

Reliability Analysis for AFTI-F16 SRFCS Using ASSIST and SURE

This paper reports the results of a study on reliability analysis of an AFTI-16 Self-Repairing Flight Control System (SRFCS) using software tools SURE (Semi-Markov Unreliability Range Evaluator and ASSIST (Abstract Semi-Markov Specification Interface to the SURE Tool). The purpose of the study is to investigate the potential utility of the software tools in the ongoing effort of the NASA Aviation Safety Program, where the class of systems must be extended beyond the originally intended serving class of electronic digital processors. The study concludes that SURE and ASSIST are applicable to reliability, analysis of flight control systems. They are especially efficient for sensitivity analysis that quantifies the dependence of system reliability on model parameters. The study also confirms an earlier finding on the dominant role of a parameter called a failure coverage. The paper will remark on issues related to the improvement of coverage and the optimization of redundancy level.

Wu, N. Eva↗

Reusable and Extensible High Level Data Distributions

This paper presents a reusable design of a data distribution framework for data parallel high performance applications. We are implementing the design in the context of the Chapel high productivity programming language. Distributions in Chapel are a means to express locality in systems composed of large numbers of processor and memory components connected by a network. Since distributions have a great effect on,the performance of applications, it is important that the distribution strategy can be chosen by a user. At the same time, high productivity concerns require that the user is shielded from error-prone, tedious details such as communication and synchronization. We propose an approach to distributions that enables the user to refine a language-provided distribution type and adjust it to optimize the performance of the application. Additionally, we conceal from the user low-level communication and synchronization details to increase productivity. To emphasize the generality of our distribution machinery, we present its abstract design in the form of a design pattern, which is independent of a concrete implementation. To illustrate the applicability of our distribution framework design, we outline the implementation of data distributions in terms of the Chapel language.

patterns↗

Space-Shuttle Emulator Software

A package of software has been developed to execute a raw binary image of the space shuttle flight software for simulation of the computational effects of operation of space shuttle avionics. This software can be run on inexpensive computer workstations. Heretofore, it was necessary to use real flight computers to perform such tests and simulations. The package includes a program that emulates the space shuttle orbiter general- purpose computer [consisting of a central processing unit (CPU), input/output processor (IOP), master sequence controller, and buscontrol elements]; an emulator of the orbiter display electronics unit and models of the associated cathode-ray tubes, keyboards, and switch controls; computational models of the data-bus network; computational models of the multiplexer-demultiplexer components; an emulation of the pulse-code modulation master unit; an emulation of the payload data interleaver; a model of the master timing unit; a model of the mass memory unit; and a software component that ensures compatibility of telemetry and command services between the simulated space shuttle avionics and a mission control center. The software package is portable to several host platforms.

Arnold, Scott↗

Processor for the UNIVAC 1100 series

MBASIC, advanced version of BASIC, is high-level interactive computer language designed to minimize time required for user to program task for computer execution. Language usually results in shorter and simpler programs that are easier to write and understand.

Bracher, F. H.↗

Three-dimensional object tracking system and method employing plural sensors and plural processors for performing parallel processing

A multiple sensor/multiple processor 3-D tracking system includes multiple sensor (camera) and DSP combinations and a controller connected so as to create a parallel computer from the multiple DSPs. The camera/DSP combinations and the controller are connected together to form a ring. For 3-D position measurement and tracking applications, each camera/DSP combination is programmed with an identical program to function as a node in a true parallel computer, and the transformation equations are solved in a distributed fashion using the entire parallel machine. The distributed processor processes the camera x and y point measurements in a distributed and parallel fashion to yield a solution to the coordinate transformation equations much more quickly than is possible with multiple camera/DSP combinations and a single processor.

Welch, Sharon S.↗

SequenceL: Automated Parallel Algorithms Derived from CSP-NT Computational Laws

With the introduction of new parallel architectures like the cell and multicore chips from IBM, Intel, AMD, and ARM, as well as the petascale processing available for highend computing, a larger number of programmers will need to write parallel codes. Adding the parallel control structure to the sequence, selection, and iterative control constructs increases the complexity of code development, which often results in increased development costs and decreased reliability. SequenceL is a high-level programming language that is, a programming language that is closer to a human s way of thinking than to a machine s. Historically, high-level languages have resulted in decreased development costs and increased reliability, at the expense of performance. In recent applications at JSC and in industry, SequenceL has demonstrated the usual advantages of high-level programming in terms of low cost and high reliability. SequenceL programs, however, have run at speeds typically comparable with, and in many cases faster than, their counterparts written in C and C++ when run on single-core processors. Moreover, SequenceL is able to generate parallel executables automatically for multicore hardware, gaining parallel speedups without any extra effort from the programmer beyond what is required to write the sequen tial/singlecore code. A SequenceL-to-C++ translator has been developed that automatically renders readable multithreaded C++ from a combination of a SequenceL program and sample data input. The SequenceL language is based on two fundamental computational laws, Consume-Simplify- Produce (CSP) and Normalize-Trans - pose (NT), which enable it to automate the creation of parallel algorithms from high-level code that has no annotations of parallelism whatsoever. In our anecdotal experience, SequenceL development has been in every case less costly than development of the same algorithm in sequential (that is, single-core, single process) C or C++, and an order of magnitude less costly than development of comparable parallel code. Moreover, SequenceL not only automatically parallelizes the code, but since it is based on CSP-NT, it is provably race free, thus eliminating the largest quality challenge the parallelized software developer faces.

Cooke, Daniel↗

Development Status of the NASA 30-cm Ion Thruster and Power Processor

Xenon ion propulsion systems are being developed by NASA Lewis Research Center and the Jet Propulsion Laboratory to provide flight qualification and validation for planetary and earth-orbital missions. In the ground-test element of this program, light-weight (less than 7 kg), 30 cm diameter ion thrusters have been fabricated, and preliminary design verification tests have been conducted. At 2.3 kW, the thrust, specific impulse, and efficiency were 91 mN, 3300 s, and 0.65, respectively. An engineering model thruster is now undergoing a 2000 h wear-test. A breadboard power processor is being developed to operate from an 80 V to 120 V power bus with inverter switching frequencies of 50 kHz. The power processor design is a pathfinder and uses only three power supplies. The projected specific mass of a flight unit is about 5 kg/kW with an efficiency of 0.92 at the full-power of 2.5 kW. Preliminary integration tests of the neutralizer power supply and the ion thruster have been completed. Fabrication and test of the discharge and beam/accelerator power stages are underway.

Sovey, James S.↗

Portable Computer Technology (PCT) Research and Development Program Phase 2

The subject of this project report, focused on: (1) Design and development of two Advanced Portable Workstation 2 (APW 2) units. These units incorporate advanced technology features such as a low power Pentium processor, a high resolution color display, National Television Standards Committee (NTSC) video handling capabilities, a Personal Computer Memory Card International Association (PCMCIA) interface, and Small Computer System Interface (SCSI) and ethernet interfaces. (2) Use these units to integrate and demonstrate advanced wireless network and portable video capabilities. (3) Qualification of the APW 2 systems for use in specific experiments aboard the Mir Space Station. A major objective of the PCT Phase 2 program was to help guide future choices in computing platforms and techniques for meeting National Aeronautics and Space Administration (NASA) mission objectives. The focus being on the development of optimal configurations of computing hardware, software applications, and network technologies for use on NASA missions.

Castillo, Michael↗

NSTAR Ion Thruster and Breadboard Power Processor Functional Integration Test Results

A 2.3 kW Breadboard Power Processing Unit (BBPPU) was developed as part of the NASA Solar Electric Propulsion Technology Application Readiness (NSTAR) Program. The NSTAR program will deliver an electric propulsion system based on a 30 cm xenon ion thruster to the New Millennium (NM) program for use as the primary propulsion system for the initial NM flight. The final development test for the BBPPU, the Functional Integration Test, was carried out to demonstrate all aspects of BBPPU operation with an Engineering Model Thruster. Test objectives included: (1) demonstration and validation of automated thruster start procedures, (2) demonstration of stable closed loop control of the thruster beam current, (3) successful response and recovery to thruster faults, and (4) successful safing of the system during simulated spacecraft faults. These objectives were met over the specified 80-120 VDC input voltage range and 0.5-2.3 output power capability of the BBPPU. Two minor anomalies were noted in discharge and neutralizer keeper current. These anomalies did not affect the stability of the system and were successfully corrected.

Hamley, John A.↗

Partial Overhaul and Initial Parallel Optimization of KINETICS, a Coupled Dynamics and Chemistry Atmosphere Model

KINETICS is a coupled dynamics and chemistry atmosphere model that is data intensive and computationally demanding. The potential performance gain from using a supercomputer motivates the adaptation from a serial version to a parallelized one. Although the initial parallelization had been done, bottlenecks caused by an abundance of communication calls between processors led to an unfavorable drop in performance. Before starting on the parallel optimization process, a partial overhaul was required because a large emphasis was placed on streamlining the code for user convenience and revising the program to accommodate the new supercomputers at Caltech and JPL. After the first round of optimizations, the partial runtime was reduced by a factor of 23; however, performance gains are dependent on the size of the data, the number of processors requested, and the computer used.

KINETICS↗

Tensor Network Quantum Virtual Machine for Simulating Quantum Circuits at Exascale

The numerical simulation of quantum circuits is an indispensable tool for development, verification, and validation of hybrid quantum-classical algorithms intended for near-term quantum co-processors. The emergence of exascale high-performance computing (HPC) platforms presents new opportunities for pushing the boundaries of quantum circuit simulation. Here, we present a modernized version of the Tensor Network Quantum Virtual Machine (TNQVM) that serves as the quantum circuit simulation backend in the eXtreme-scale ACCelerator (XACC) framework. The new version is based on the scalable tensor network processing library ExaTN (Exascale Tensor Networks). It provides multiple configurable quantum circuit simulators that perform either an exact quantum circuit simulation via the full tensor network contraction or an approximate simulation via a suitably chosen tensor factorization scheme. Upon necessity, stochastic noise modeling from real quantum processors is incorporated into the simulations by modeling quantum channels with Kraus tensors. By combining the portable XACC quantum programming frontend and the scalable ExaTN numerical processing backend, we introduce an end-to-end virtual quantum development environment that can scale from laptops to future exascale platforms. We report initial benchmarks of our framework, which include a demonstration of the distributed execution, incorporation of quantum decoherence models, and simulation of the random quantum circuits used for the certification of quantum supremacy on Google’s Sycamore superconducting architecture.

Nguyen, Thien↗

Numerical interactive controller

Device allows interaction of operator with data in computer central processor in order to shift frame of data in Cartesian coordinates and slew desired data into view. ''Cursor generator program,'' in conjunction with device, provides light pen with sufficient resolving power to identify any particular set of coordinates with single-cell accuracy.

Brokl, S. S.↗

Endurance testing of a 30-cm Kaufman thruster

Results of a program to demonstrate lifetime capability of a 30-cm Kaufman ion thruster with a 6000 hour endurance test are described. Included in the program are (1) thruster fabrication, (2) design and construction of a test console containing a transistorized high frequency power processor, and control circuits which provide unattended automatic operation of the thruster, and (3) modification of a vacuum facility to incorporate a frozen mercury collector and permit unattended operation. Four tests ranging in duration from 100 to 1100 hours have been completed. These tests and the resulting thruster modifications are described. The status of the endurance test is also presented.

Collett, C. R.↗

Instructional image processing on a university mainframe: The Kansas system

An interactive digital image processing program package was developed that runs on the University of Kansas central computer, a Honeywell Level 66 multi-processor system. The module form of the package allows easy and rapid upgrades and extensions of the system and is used in remote sensing courses in the Department of Geography, in regional five-day short courses for academics and professionals, and also in remote sensing projects and research. The package comprises three self-contained modules of processing functions: Subimage extraction and rectification; image enhancement, preprocessing and data reduction; and classification. Its use in a typical course setting is described. Availability and costs are considered.

Williams, T. H. L.↗

Computer sciences

The Computer Science Program provides advanced concepts, techniques, system architectures, algorithms, and software for both space and aeronautics information sciences and computer systems. The overall goal is to provide the technical foundation within NASA for the advancement of computing technology in aerospace applications. The research program is improving the state of knowledge of fundamental aerospace computing principles and advancing computing technology in space applications such as software engineering and information extraction from data collected by scientific instruments in space. The program includes the development of special algorithms and techniques to exploit the computing power provided by high performance parallel processors and special purpose architectures. Research is being conducted in the fundamentals of data base logic and improvement techniques for producing reliable computing systems.

Smith, Paul H.↗