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At least 559 records · Page 31

Real-time processor for staring receivers

The design, fabrication, and testing of a state-of-the-art, high-throughput on-focal plane IR-image signal processor is described. The processing functions performed are frame differencing and thresholding. The final focal plane array will consist of a 128 x 128-pixel platinum-silicide detector bump-mounted to an on-chip CCD multiplexer. The processor is in a 128-channel parallel-pipeline format. Each channel consists of a pixel regenerator (charge differencer), 128-pixel frame store CCD memory, pixel differencer, second pixel regenerator, thresholder (analog comparator), and digital latch. Four parallel analog outputs and four parallel digital outputs are included. The digital outputs provide a bit map of the image. All analog clock signals (128 KHz, 256 KHz, and 5 MHz) are generated by on-chip TTL-input clock drivers. TTL clock driver inputs are generated off-chip. The technology is low-temperature surface and buried channel CCD/CMOS/indium bump. The design goal was 8-bit resolution at 77 K and 1000 frames/s. Applications include point- or extended-target motion detection with thresholding. Design trade-offs and enhancements (such as on-chip detector gain compensation and a simple window processor) are discussed.

Hanzal, Brian↗

Post-game analysis: An initial experiment for heuristic-based resource management in concurrent systems

In concurrent systems, a major responsibility of the resource management system is to decide how the application program is to be mapped onto the multi-processor. Instead of using abstract program and machine models, a generate-and-test framework known as 'post-game analysis' that is based on data gathered during program execution is proposed. Each iteration consists of (1) (a simulation of) an execution of the program; (2) analysis of the data gathered; and (3) the proposal of a new mapping that would have a smaller execution time. These heuristics are applied to predict execution time changes in response to small perturbations applied to the current mapping. An initial experiment was carried out using simple strategies on 'pipeline-like' applications. The results obtained from four simple strategies demonstrated that for this kind of application, even simple strategies can produce acceptable speed-up with a small number of iterations.

Yan, Jerry C.↗

Real-Time Reed-Solomon Decoder

Generic Reed-Solomon decoder fast enough to correct errors in real time in practical applications designed to be implemented in fewer and smaller very-large-scale integrated, VLSI, circuit chips. Configured to operate in pipelined manner. One outstanding aspect of decoder design is that Euclid multiplier and divider modules contain Galoisfield multipliers configured as combinational-logic cells. Operates at speeds greater than older multipliers. Cellular configuration highly regular and requires little interconnection area, making it ideal for implementation in extraordinarily dense VLSI circuitry. Flight electronics single chip version of this technology implemented and available.

Maki, Gary K.↗

New Remote Gas Sensor Using Rapid Electro-Optical Path Switching

Innovative gas filter correlation radiometer (GFCR) features nonmechanical switching of internal optical paths. Incoming radiation switched electro-optically, by means of polarization, between two optical paths, one of which contains correlation gas cell while other does not. Advantages include switching speed, 2 to 3 orders of magnitude faster than mechanical techniques, and high reliability. Applications include regional studies of atmospheric chemistry from either manned or unmanned aircraft as well as satellite studies of global distributions, sources and sink mechanisms for key species involved in chemistry of troposphere. Commercial applications: ability to survey many miles of natural gas pipelines rapidly from aircraft, pinpointing gas leaks by measuring methane at 2.3 micrometers.

Sachse, G. W.↗

On-orbit servicing for USAF space missions: A phased development approach

On-orbit servicing has been studied for years by the U.S. Air Force Space Systems Division--which recently cosponsored the Space Assembly, Maintenance, and Servicing Study with NASA and SDIO; but an Air force servicing program has yet to emerge. The Air Force has a limited set of servicing requirements, and the practices of 'pipelining' (incremental improvements to a space vehicle series) and orbital sparing provide many similar benefits. It is postulated that an Air Force Program will be initiated in response to a new critical mission requirement that calls for a spacecraft with the operational character of a Servicer, which will evolve into a servicing program. Such a requirement may be emerging. The Air Force organizations charged with on-orbit test safety for the Department of Defense are concerned with the hazard from uncontrolled reentry of low Earth orbit test spacecraft, which are increasing in number. Analysis and observations of actual reentries show that debris reaches the Earth's surface. A phased development of a system to remove these spacecraft from orbit can evolve into a servicing program.

Shanney, Bill↗

Low power signal processing research at Stanford

This paper gives an overview of the research being conducted at Stanford University's Space, Telecommunications, and Radioscience Laboratory in the area of low energy computation. It discusses the work we are doing in large scale digital VLSI neural networks, interleaved processor and pipelined memory architectures, energy estimation and optimization, multichip module packaging, and low voltage digital logic.

Burr, J.↗

Simplified microprocessor design for VLSI control applications

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

Cameron, K.↗

Avoiding and tolerating latency in large-scale next-generation shared-memory multiprocessors

A scalable solution to the memory-latency problem is necessary to prevent the large latencies of synchronization and memory operations inherent in large-scale shared-memory multiprocessors from reducing high performance. We distinguish latency avoidance and latency tolerance. Latency is avoided when data is brought to nearby locales for future reference. Latency is tolerated when references are overlapped with other computation. Latency-avoiding locales include: processor registers, data caches used temporally, and nearby memory modules. Tolerating communication latency requires parallelism, allowing the overlap of communication and computation. Latency-tolerating techniques include: vector pipelining, data caches used spatially, prefetching in various forms, and multithreading in various forms. Relaxing the consistency model permits increased use of avoidance and tolerance techniques. Each model is a mapping from the program text to sets of partial orders on program operations; it is a convention about which temporal precedences among program operations are necessary. Information about temporal locality and parallelism constrains the use of avoidance and tolerance techniques. Suitable architectural primitives and compiler technology are required to exploit the increased freedom to reorder and overlap operations in relaxed models.

Probst, David K.↗

Low-latency digital frequency synthesizer using the residue number system

A low-latency frequency synthesizer using the Direct Digital Synthesis (DDS) technique has been designed. Called the Residue Assisted Frequency Synthesizer (RAFS), it exhibits frequency switching times which are reduced by more than 50 percent below previously published designs. The switching speed advantage is made possible by the use of the Residue Number System, which allows the pipeline lengths in the Phase Accumulator and other circuitry to be reduced significantly.

Chren, William A., Jr.↗

High-speed Viterbi decoding with overlapping code sequences

The Viterbi Algorithm for decoding convolutional codes and Trellis Coded Modulation is suited to VLSI implementation but contains a feedback loop which limits the speed of pipelined architecture. The feedback loop is circumvented by decoding independent sequences simultaneously, resulting in a 5-9 fold speed-up with a two-fold hardware expansion.

Ross, Michael D.↗

Evaluation of floating-point sum or difference of products in carry-save domain

An architecture to evaluate a 24-bit floating-point sum or difference of products using modified sequential carry-save multipliers with extensive pipelining is described. The basic building block of the architecture is a carry-save multiplier with built-in mantissa alignment for the summation during the multiplication cycles. A carry-save adder, capable of mantissa alignment, correctly positions products with the current carry-save sum. Carry propagation in individual multipliers is avoided and is only required once to produce the final result.

Wahab, A.↗

A statistical-based scheduling algorithm in automated data path synthesis

In this paper, we propose a new heuristic scheduling algorithm based on the statistical analysis of the cumulative frequency distribution of operations among control steps. It has a tendency of escaping from local minima and therefore reaching a globally optimal solution. The presented algorithm considers the real world constraints such as chained operations, multicycle operations, and pipelined data paths. The result of the experiment shows that it gives optimal solutions, even though it is greedy in nature.

Jeon, Byung Wook↗

Instruction set commutivity

We present a state property called congruence and show how it can be used to demonstrate commutivity of instructions in a modern load-store architecture. Our analysis is particularly important in pipelined microprocessors where instructions are frequently reordered to avoid costly delays in execution caused by hazards. Our work has significant implications to safety and security critical applications since reordering can easily change the meaning and an instruction sequence and current techniques are largely ad hoc. Our work is done in a mechanical theorem prover and results in a set of trustworthy rules for instruction reordering. The mechanization makes it practical to analyze the entire instruction set.

Windley, P.↗

A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

Timoc, C.↗

The European Southern Observatory-MIDAS table file system

The new and substantially upgraded version of the Table File System in MIDAS is presented as a scientific database system. MIDAS applications for performing database operations on tables are discussed, for instance, the exchange of the data to and from the TFS, the selection of objects, the uncertainty joins across tables, and the graphical representation of data. This upgraded version of the TFS is a full implementation of the binary table extension of the FITS format; in addition, it also supports arrays of strings. Different storage strategies for optimal access of very large data sets are implemented and are addressed in detail. As a simple relational database, the TFS may be used for the management of personal data files. This opens the way to intelligent pipeline processing of large amounts of data. One of the key features of the Table File System is to provide also an extensive set of tools for the analysis of the final results of a reduction process. Column operations using standard and special mathematical functions as well as statistical distributions can be carried out; commands for linear regression and model fitting using nonlinear least square methods and user-defined functions are available. Finally, statistical tests of hypothesis and multivariate methods can also operate on tables.

Peron, M.↗

The ISO SWS on-line system

The software which is currently being developed for the Short Wavelength Spectrometer (SWS) of the Infrared Space Observatory (ISO) is described. The spectrometer has a wide range of capabilities in the 2-45 micron infrared band. SWS contains two independent gratings, one for the long and one for the short wavelength section of the band. With the gratings a spectral resolution of approximately 1000 to approximately 2500 can be obtained. The instrument also contains two Fabry-Perault's yielding a resolution between approximately 1000 and approximately 20000. Software is currently being developed for the acquisition, calibration, and analysis of SWS data. The software is firstly required to run in a pipeline mode without human interaction, to process data as they are received from the telescope. However, both for testing and calibration of the instrument as well as for evaluation of the planned operating procedures the software should also be suitable for interactive use. Thirdly the same software will be used for long term characterization of the instrument. The software must work properly within the environment designed by the European Space Agency (ESA) for the spacecraft operations. As a result strict constraints are put on I/O devices, throughput etc.

Roelfsema, P. R.↗

The Seventh Annual National Conference of Black Physics Students

The National Conference of Black Physics Students began in 1986 when several Black physics graduate students at MIT and Harvard decided to address the 'pipeline problem' of African Americans in physics by organizing a conference for Black physics undergraduates. The goals of the conference were: (1) to develop a network within the Black physics community, (2) to make Black students in physics, particularly at graduate level, aware of academic and professional opportunities and (3) to bring important issues and developments in the field to the attention of these students. We are pleased to announce the Seventh Annual National Conference of Black Physics Students held February 12 and 13, 1993 served the largest population of students so far. The largest conference previous to this one hosted 150 students. We registered and prepared for 240 students with 210 actually attenting. We received so many qualified abstracts for technical talks by students that instead of NCBPS's tradition of 3-4 student presentations, we ran 4 parallel sessions in different rooms with 4-5 presentations in each room. In response to comments from previous conferences, the program contained 3 workshop/discussion sessions. The topics for the interactive discussion workshops were: 'Getting Ready for Graduate School,' 'How to Succeed in Graduate School,' and 'Issues Facing Black Scientists.'

Crawley, Gerard M.↗

Photovoltaic power without batteries for continuous cathodic protection

The COASTSYSTA designed, installed, and started up on 20 Jan. 1990, a state-of-the-art stand alone photovoltaic powered impressed current cathodic protection system (PVCPSYS) not requiring any auxiliary/battery backup power for steel and iron submerged structures. The PVCPSYS installed on 775' of steel sheet piling of a Navy bulkhead is continuing to provide complete, continuous corrosion protection. This has been well documented by COASTSYSTA and verified on-site by the U.S. Army Civil Engineering Research Laboratory, Champaign, Illinois and the Navy Energy Program Office-Photovoltaic Programs, China Lake, California. The Department of Defense (DoD) Photovoltaic Review Committee and Sandia National Laboratories consider this successful and cost effective system a major advance in the application of photovoltaic power. The PVCPSYS uses only renewable energy and is environmentally clean. A patent is pending on the new technology. Other possible PVCPSYS applications are mothballed ships, docks, dams, locks, bridges, marinas, offshore structures, and pipelines. The initial cost savings by installing a PVCPSYS vs. a conventional CP system was in excess of $46,000.00.

Muehl, W. W., Sr.↗