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At least 559 records · Page 31
All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

Foreign Object Damage in a Gas-Turbine Grade Silicon Nitride by Spherical Projectiles of Various Materials

Assessments of foreign object damage (FOD) of a commercial, gas-turbine grade, in situ toughened silicon nitride ceramic (AS800, Honeywell Ceramics Components) were made using four different projectile materials at ambient temperature. AS800 flexure target specimens rigidly supported were impacted at their centers in a velocity range from 50 to 450 m/s by spherical projectiles with a diameter of 1.59 mm. Four different projectile materials were used including hardened steel, annealed steel, silicon nitride ceramic, and brass. Post-impact strength of each target specimen impacted was determined as a function of impact velocity to appraise the severity of local impact damage. For a given impact velocity, the degree of strength degradation was greatest for ceramic balls, least for brass balls, and intermediate for annealed and hardened steel balls. For steel balls, hardened projectiles yielded more significant impact damage than annealed counterparts. The most important material parameter affecting FOD was identified as hardness of projectiles. Impact load as a function of impact velocity was quasi-statically estimated based on both impact and static indentation associated data.

Choi, Sung R.↗
NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗
NASA NTRS2008

Progress in Development of Improved Ion-Channel Biosensors

Further improvements have recently been made in the development of the devices described in Improved Ion-Channel Biosensors (NPO-30710), NASA Tech Briefs, Vol. 28, No. 10 (October 2004), page 30. As discussed in more detail in that article, these sensors offer advantages of greater stability, greater lifetime, and individual electrical addressability, relative to prior ion-channel biosensors. In order to give meaning to a brief description of the recent improvements, it is necessary to recapitulate a substantial portion of the text of the cited previous article. The figure depicts one sensor that incorporates the recent improvements, and can be helpful in understanding the recapitulated text, which follows: These sensors are microfabricated from silicon and other materials compatible with silicon. Typically, the sensors are fabricated in arrays in silicon wafers on glass plates. Each sensor in the array can be individually electrically addressed, without interference with its neighbors. Each sensor includes a well covered by a thin layer of silicon nitride, in which is made a pinhole for the formation of a lipid bilayer membrane. In one stage of fabrication, the lower half of the well is filled with agarose, which is allowed to harden. Then the upper half of the well is filled with a liquid electrolyte (which thereafter remains liquid) and a lipid bilayer is painted over the pinhole. The liquid contains a protein that forms an ion channel on top of the hardened agarose. The combination of enclosure in the well and support by the hardened agarose provides the stability needed to keep the membrane functional for times as long as days or even weeks. An electrode above the well, another electrode below the well, and all the materials between the electrodes together constitute a capacitor. What is measured is the capacitive transient current in response to an applied voltage pulse. One notable feature of this sensor, in comparison with prior such sensors, is a relatively thick dielectric layer between the top of the well and the top electrode. This layer greatly reduces the capacitance of an aperture across which the ion channels are formed, thereby increasing the signal-to-noise ratio. The use of a relatively large aperture with agarose support makes it possible to form many ion channels instead of only one, thereby further increasing the signal-to-noise ratio and effectively increasing the size of the available ionic reservoir. The relatively large reservoir makes it possible to measure AC rather than DC. This concludes the recapitulation from the cited previous article.

Nadeau, Jay L.↗
NASA NTRS2010

SEU/SET Tolerant Phase-Locked Loops

The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!

Shuler, Robert L., Jr.↗
NASA NTRS2010

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for the Federal fiscal year of 2010 are: Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments, Modeling of Radiation Effects on Electronics, Radiation Hardened High Performance Processors (HPP), and and Reconfigurable Computing.

Keys, Andrew S.↗
NASA NTRS2010

Re-Verification of the IRHN57133SE and IRHN57250SE for Single Event Gate Rupture and Single Event Burnout

The vertical metal oxide semiconductor field-effect transistor (MOSFET) is a widely used power transistor onboard a spacecraft. The MOSFET is typically employed in power supplies and high current switching applications. Due to the inherent high electric fields in the device, power MOSFETs are sensitive to heavy ion irradiation and can fail catastrophically as a result of single event gate rupture (SEGR) or single event burnout (SEB). Manufacturers have designed radiation-hardened power MOSFETs for space applications. These radiation hardened devices are not immune to SEGR or SEB but, rather, can exhibit them at a much more damaging ion than their non-radiation hardened counterparts. See [1] through [5] for more information.This effort was to investigate the SEGR and SEB responses of two power MOSFETs from IR(the IRHN57133SE and the IRHN57250SE) that have recently been produced on a new fabrication line. These tests will serve as a limited verification of these parts, but it is acknowledged that further testing on the respective parts may be needed for some mission profiles.

Single Event Gate Rupture (SEGR)↗
NASA NTRS2011

Fault-Tolerant, Radiation-Hard DSP

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Czajkowski, David↗
NASA NTRS2011

Experiment in Onboard Synthetic Aperture Radar Data Processing

Single event upsets (SEUs) are a threat to any computing system running on hardware that has not been physically radiation hardened. In addition to mandating the use of performance-limited, hardened heritage equipment, prior techniques for dealing with the SEU problem often involved hardware-based error detection and correction (EDAC). With limited computing resources, software- based EDAC, or any more elaborate recovery methods, were often not feasible. Synthetic aperture radars (SARs), when operated in the space environment, are interesting due to their relevance to NASAs objectives, but problematic in the sense of producing prodigious amounts of raw data. Prior implementations of the SAR data processing algorithm have been too slow, too computationally intensive, and require too much application memory for onboard execution to be a realistic option when using the type of heritage processing technology described above. This standard C-language implementation of SAR data processing is distributed over many cores of a Tilera Multicore Processor, and employs novel Radiation Hardening by Software (RHBS) techniques designed to protect the component processes (one per core) and their shared application memory from the sort of SEUs expected in the space environment. The source code includes calls to Tilera APIs, and a specialized Tilera compiler is required to produce a Tilera executable. The compiled application reads input data describing the position and orientation of a radar platform, as well as its radar-burst data, over time and writes out processed data in a form that is useful for analysis of the radar observations.

Holland, Matthew↗
NASA NTRS2012

SpaceCube Mini

This version of the SpaceCube will be a full-fledged, onboard space processing system capable of 2500+ MIPS, and featuring a number of plug-andplay gigabit and standard interfaces, all in a condensed 3x3x3 form factor [less than 10 watts and less than 3 lb (approximately equal to 1.4 kg)]. The main processing engine is the Xilinx SIRF radiation- hardened-by-design Virtex-5 FX-130T field-programmable gate array (FPGA). Even as the SpaceCube 2.0 version (currently under test) is being targeted as the platform of choice for a number of the upcoming Earth Science Decadal Survey missions, GSFC has been contacted by customers who wish to see a system that incorporates key features of the version 2.0 architecture in an even smaller form factor. In order to fulfill that need, the SpaceCube Mini is being designed, and will be a very compact and low-power system. A similar flight system with this combination of small size, low power, low cost, adaptability, and extremely high processing power does not otherwise exist, and the SpaceCube Mini will be of tremendous benefit to GSFC and its partners. The SpaceCube Mini will utilize space-grade components. The primary processing engine of the Mini is the Xilinx Virtex-5 SIRF FX-130T radiation-hardened-by-design FPGA for critical flight applications in high-radiation environments. The Mini can also be equipped with a commercial Xilinx Virtex-5 FPGA with integrated PowerPCs for a low-cost, high-power computing platform for use in the relatively radiation- benign LEOs (low-Earth orbits). In either case, this version of the Space-Cube will weigh less than 3 pounds (.1.4 kg), conform to the CubeSat form-factor (10x10x10 cm), and will be low power (less than 10 watts for typical applications). The SpaceCube Mini will have a radiation-hardened Aeroflex FPGA for configuring and scrubbing the Xilinx FPGA by utilizing the onboard FLASH memory to store the configuration files. The FLASH memory will also be used for storing algorithm and application code for the PowerPCs and the Xilinx FPGA. In addition, it will feature highspeed DDR SDRAM (double data rate synchronous dynamic random-access memory) to store the instructions and data of active applications. This version will also feature SATA-II and Gigabit Ethernet interfaces. Furthermore, there will also be general-purpose, multi-gigabit interfaces. In addition, the system will have dozens of transceivers that can support LVDS (low-voltage differential signaling), RS-422, or SpaceWire. The SpaceCube Mini includes an I/O card that can be customized to meet the needs of each mission. This version of the SpaceCube will be designed so that multiple Minis can be networked together using SpaceWire, Ethernet, or even a custom protocol. Scalability can be provided by networking multiple SpaceCube Minis together. Rigid-Flex technology is being targeted for the construction of the SpaceCube Mini, which will make the extremely compact and low-weight design feasible. The SpaceCube Mini is designed to fit in the compact CubeSat form factor, thus allowing deployment in a new class of missions that the previous SpaceCube versions were not suited for. At the time of this reporting, engineering units should be available in the summer 2012.

Michael Lin↗
NASA NTRS2012

Mitigating Abnormal Grain Growth for Friction Stir Welded Al-Li 2195 Spun Formed Domes

Formability and abnormal grain growth (AGG) are the two major issues that have been encountered for Al alloy spun formed dome development using friction stir welded blanks. Material properties that have significant influence on the formability include forming range and strain hardening exponent. In this study, tensile tests were performed for two 2195 friction stir weld parameter sets at 400 F to study the effects of post weld anneal on the forming range and strain hardening exponent. It was found that the formability can be enhanced by applying a newly developed post weld anneal to heat treat the friction stir welded panels. This new post weld anneal leads to a higher forming range and much improved strain hardening exponent. AGG in the weld nugget is known to cause a significant reduction of ductility and fracture toughness. This study also investigated how AGG may be influenced by the heating rate to the solution heat treatment temperature. After post-weld annealing, friction stir welds were strained to 15% and 39% by compression at 400 F before they were subjected to SHT at 950 F for 1 hour. Salt bath SHT is very effective in reducing the grain size as it helps arrest the onset of AGG and promote normal recrystallization and grain growth. However, heat treating a 18 ft dome using a salt bath is not practical. Efforts are continuing at Marshall Space Flight Center to identify the welding parameters and heat treating parameters that can help mitigate the AGG in the friction stir welds.

Chen, Po-Shou↗
NASA NTRS2012

Charpy Impact Energy and Microindentation Hardness of 60-NITINOL

60-NITINOL (60 wt.% Ni 40 wt.% Ti) is being studied as a material for advanced aerospace components. The Charpy impact energy and microindentation hardness has been studied for this material, fabricated by vacuum induction skull melting (casting) and by hot isostatic pressing. Test specimens were prepared in various hardened and annealed heat treatment conditions. The average impact energy ranged from 0.33 to 0.49J for the hardened specimens while the annealed specimens had impact energies ranging from 0.89 to 1.18J. The average hardness values of the hardened specimens ranged from 590 to 676 HV while that of the annealed specimens ranged from 298 to 366 HV, suggesting an inverse relationship between impact energy and hardness. These results are expected to provide guidance in the selection of heat treatment processes for the design of mechanical components.

Stanford, Malcolm K.↗
NASA NTRS2010

Localized Triple Modular Redundancy vs. Distributed Triple Modular Redundancy on a ProASIC3E Reprogrammable FPGA

Field programmable gate arrays (FPGA) are used in every space application. Currently, most space flight applications use radiation hardened (RH) FPGAs, which are very expensive. There is a desire to use cheaper, commercial off the shelf reprogrammable FPGAs, which are more susceptible to radiation effects known as single-event effects (SEE). The RH parts have SEE and total ionizing dose (TID) hardened elements pre-integrated into the part. This means that the designer does not need to implement any hardening techniques while configuring the device. The COTS parts on the other hand must be mitigated by design in order to insure any form of mitigation. The design techniques this project examines concern the use of localized triple modular redundancy (LTMR) and distributed triple modular redundancy (DTMR). LTMR triples every flip flop in the device architecture while DTMR triples everything except for the global routes (clocks, resets, and enables). The testing was performed on a ProASIC3E FPGA at the Texas A&M cyclotron facility. Two design architectures were used: shift registers and counters, both with LTMR and DTMR mitigation techniques. The test results prove that DTMR is more effective at reducing SEE than LTMR. We also determined that there was not a significant difference between the use of shift registers and counters for test purposes. More testing is required to obtain additional linear energy transfer values for each architecture and mitigation technique in order to determine the most cost-effective method of SEE mitigation.

McGuffey, Alex↗
NASA NTRS2019

Automated Grain Yield Behavior Classification

A method for classifying grain stress evolution behaviors using unsupervised learning techniques is presented. The method is applied to analyze grain stress histories measured in-situ using high-energy X-ray diffraction microscopy (HEDM) from the aluminum-lithium alloy Al-Li 2099 at the elastic-plastic transition (yield). The unsupervised learning process automatically classified the grain stress histories into four groups: major softening, no work-hardening or softening, moderate work-hardening, and major work-hardening. The orientation and spatial dependence of these four groups are discussed. In addition, the generality of the classification process to other samples is explored.

Pagan, Darren C↗
NASA NTRSDate not supplied

Making Thin Sections from National Treasures: A Little Moon Rock Goes a Long Way

NASA’s Johnson Space Center curates the Apollo sample collection through their facilities in Houston, TX. It is a dual-purpose facility, intended both to store and preserve the precious samples, as well as to make them available for ongoing scientific study and public examination. The facilities consist of multiple vaults and lab spaces, including the Apollo Thin Section Lab. Although it is a part of the Curation facilities, this lab is intended to process specific lunar rock and dust samples into what are called “thin sections”. A thin section is a microscope slide with a very thin, highly polished slice of rock material mounted on it. These are used not only for microscope viewing, but also for a range of other sophisticated scientific instruments to map and measure fine details of the rock’s physical and chemical composition and structure. The process of making a thin section requires great care and patience and is an art in itself; each one is unique, and each sample can behave very differently while going through the same basic procedures. In general, it begins by taking a small chip of rock from a much larger sample. The rock fragment is placed within a small mold and liquid epoxy is poured over it and allowed to harden, producing what is called a “potted butt” (Figure 1). This is to stabilize the rock so that it won’t fragment or crumble during polishing, and to fill any cracks or voids within the rock. Once hardened, the epoxy on the bottom is carefully ground away to expose the rock surface within, which is then polished to a 1-micron finish. A thin new layer of fresh epoxy is then applied to the polished surface and used to mount it to a silica slide. Once the mounting epoxy has hardened, the potted butt is cut off less than one millimeter above the slide using a low-speed circular saw. This thin layer of sample material attached to the slide undergoes further grinding and polishing, typically bringing the sample thickness down to about 35 microns – roughly one third of the thickness of a human hair. The remaining potted butt is saved for future scientific investigations and can be re-polished and used again until all the rock material within it is used up. A single thin section can be reused countless times by numerous different researchers. In addition, thin sections are often exquisitely beautiful (Figure 2) and in some cases, lunar thin sections are used as public display samples, such as at the Smithsonian Air and Space Museum in Washington, DC. The production of thin sections allows an immense variety of research to be conducted on a tiny amount of rock or mineral material, allowing the bulk of the Apollo collection to stay pristine and unaltered, and thus, remain available for next generation of lunar scientists to further our insight into the Moon’s geological diversity, and to bring valuable new insights to our understanding of the origin of the Earth-Moon system.

J J Kent↗
DOE OSTI2022

High-Throughput Ion Irradiation and Microstructural Characterization of Multi-Principal-Element Alloys

Multi-principal-element alloys (MPEAs) have garnered interest in the nuclear community for their apparent resistance to microstructural damage under irradiation. While both experimentation and simulation have demonstrated reduced hardening and void swelling in MPEAs, the relationship between composition and irradiation response is still poorly understood since a rich experimental database for MPEAs does not yet exist. In this work, to accelerate the generation of experimental irradiation-response data for MPEAs, high-throughput synthesis, irradiation, and characterization techniques have been employed. Specifically, additive manufacturing has been used to produce arrays of various MPEAs (1-cm2 coupons), which have been subsequently irradiated using 4-MeV Ni2+ ions to a peak damage of 200 dpa at 500 °C. Hardening and void swelling have been assessed using nanoindentation and trenching via plasma focused ion beam (PFIB), respectively. Trends in the experimental data relating hardening and void swelling behavior to composition have been analyzed using different machine learning approaches.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Mechanical Behavior of Neutron Irradiated Refractory Multi-Principal Element Alloys Processed via Spark Plasma Sintering

The search for advanced materials capable of withstanding the extreme conditions of Generation IV reactors is a critical area in materials science research. These reactors operate under severe environments, including high temperatures, corrosion, stress, and irradiation damage. Consequently, there is a need for innovative alloy systems to ensure the reliability and longevity of proposed Generation IV reactor components. Refractory multi-principal-element alloys (RMPEA) have emerged as a promising candidate due to their exceptional properties. These alloys, characterized by their composition of multiple principal elements in near-equiatomic ratios, exhibit superior resistance to irradiation damage, reduced void swelling, enhanced microstructural stability, and minimal irradiation-induced hardening. While initial studies on RMPEAs have shown promising results, most research has been limited to thin films, nanocrystalline microstructures, and ion irradiation, which do not accurately represent the behavior of bulk materials. To address this gap, our research focused on the neutron irradiation of bulk RMPEAs. We aim to conduct comprehensive post-irradiation examinations (PIE) of RMPEAs irradiated at the Advanced Test Reactor at Idaho National Laboratory. The RMPEAs were synthesized using spark plasma sintering (SPS) with mechanically alloyed metallurgical powder. The RMPEA specimens are a MoNbTi alloy system with additions of -Zr, and -ZrV. Furthermore, PIE consisted of mechanical testing and advanced materials characterization. The mechanical testing consisted of sub-sized tensile testing, micro- and nano- indentation. Microstructural characterization included scanning electron microscopy and transmission electron microscopy. Mechanical testing coupled with advanced microscopy techniques provides insight into phase morphology and its effects on the mechanical properties of the RMPEA specimens. The results indicate that both pristine and irradiated RMPEA specimens exhibited brittle behavior during tensile testing, which can be attributed to their heterogeneous microstructure. The SPS manufacturing process did not include any post treatment, which resulted in a heterogeneous microstructure. Energy-dispersive X-ray spectroscopy revealed the presence of intermetallic such as laves phases within the microstructure. Specifically, Ti-rich precipitates were observed in the MoNbTi specimen, while Mo-rich precipitates were found in the MoNbTiZrV specimen. Nano-hardness testing of pristine samples showed that the laves phases exhibited higher hardness values compared to the matrix phase, suggesting that precipitate hardening is likely the dominant hardening mechanism in these specimens. The results from this work will be used to build a finite element model to predict mechanical behavior of future MPEA compositions. Thus, enabling for a streamlined approach to developing novel MPEAs for the nuclear industry.

36 - MATERIALS SCIENCE↗
DOE OSTI2021

Capillary flow in UHPFRC with synthetic fibers, under high tensile stresses

A novel Ultra High-Performance Fiber Reinforced Concrete (UHPFRC) mix with synthetic fibers and a low clinker matrix, henceforth referred to as PE-UHPFRC, has been developed for structural applications. It exhibits a high tensile elastic limit above 7 MPa, a tensile strength of more than 10 MPa, and a very high tensile hardening domain of above 3.5%. In order to effectively use this material, its protective properties have been investigated on the basis of the effect of tensile deformation and subsequent cracking on water transport properties, for a wide range of tensile strain. A special setup was developed to measure the capillary absorption of liquids while the specimen is under tension. The results show a considerable reduction in capillary absorption in case of PE-UHPFRC compared with Strain Hardening Cement-based Composites (SHCC). Moreover, the results highlight the considerable effect of the onset of cracking on capillary absorption.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Air entraining admixtures: Mechanisms, evaluations, and interactions

Air entraining admixtures (AEAs) are surfactant-based solutions and powders that are used to stabilize air voids in cement paste that protect concrete against frost damage. After reviewing the chemical and structural features of AEA that govern their performance, we discuss: (i) how they establish a stabilizing shell around air voids, (ii) methods for quantifying the distribution of voids after mixing and after hardening, (iii) mechanisms by which voids protect against frost damage, (iv) effects of AEA on other properties of wet and hardened concrete, and (v) interactions of AEA with other chemical and supplementary cementitious materials.

36 MATERIALS SCIENCE↗