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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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543 records · Page 31
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

VLSI neuroprocessors

Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional techniques and enables multiple assignments, (many to many), not achievable with standard statistical approaches. Tactical movement planning (finding the best path from A to B) is accomplished with a digital two-dimensional concurrent processor array. By exploiting the natural parallel decomposition of the problem in silicon, a four order of magnitude speed-up over optimized software approaches has been demonstrated.

Kemeny, Sabrina E.↗
NASA NTRS2013

Minimal Power Latch for Single-Slope ADCs

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Hancock, Bruce R.↗
DOE OSTI2023

(U) A General-Purpose Code for Correlated Sampling Using Batch Statistics with MCNP6 for Fixed-Source Problems

Correlated sampling can be used to reduce the uncertainty of a difference of tallies by taking advantage of the negative covariance term in the sandwich formula. Booth first showed how correlated sampling can be applied with batch statistics using MCNP’s tally fluctuation chart (TFC) to reduce the uncertainty of a difference of tallies in fixed-source problems. Booth presented a problem in which a 1273% uncertainty in a difference was reduced to 8% by accounting for correlations. Researchers He and Su recently studied correlated sampling using the TFC in MCNP version 5. They determined that the code did not print enough digits in the TFC tally means for accurate batch statistics in some cases. After modifying the source code, they concluded that “correlated sampling can yield a standard deviation of about one magnitude smaller than that predicted by the direct, un-correlated simulation when the changes in system response are small (say about 1%), which is equivalent to saving in CPU time by a factor of 100. Such saving [sic] becomes less significant as the change in system response becomes larger.” He and Su provided the formulas needed to apply batch statistics to compute the correlated uncertainty of a difference of tallies. In this report, we follow up on their work by providing the formulas needed to apply batch statistics to compute the correlated uncertainty of a ratio of tallies and of a difference of two tallies divided by a third tally. We extend these formulas to differences and ratios of ratios. These formulas are applied to reduce the uncertainty associated with calculating a relative sensitivity. He and Su did not investigate the accuracy of their correlated sampling uncertainty estimates. We use their test problems and evaluate the accuracy of the uncertainty estimates by comparing with results obtained from random sampling, and, in simple cases, with theoretical values of the “exact” uncertainties. We find that the uncertainties obtained from batch statistics are accurate as long as at least 100 batches are used. We present a new computer code, COSUBS (COrrelated Sampling Using Batch Statistics), that reads MCNP6 TFCs and applies correlated sampling using batch statistics for the tally combinations that the user specifies. COSUBS is a very general tool that compares all TFCs for a base case and one or two perturbed cases. It computes uncertainties for ratios if given only a base case. This report is organized as follows. The equations to apply batch statistics to the difference of random tallies are reviewed in Sec. II. Section III presents the equations for applying batch statistics to a ratio of random tallies; this is useful for computing relative sensitivities using a one-sided finite difference and the relative sensitivity using the differential operator method. Section IV presents the equations for applying batch statistics to a difference of two random tallies divided by a third; this is useful for computing a relative sensitivities using a central difference. Section V presents the equations for applying batch statistics to a difference of two ratios with four random tallies. Section VI presents the equations for applying batch statistics to a one-sided finite difference estimate of the relative sensitivity of a ratio (this uses four random tallies). Section VII presents the equations for applying batch statistics to a central difference estimate of the relative sensitivity of a ratio (this uses six random tallies). Section VIII presents the equations for applying batch statistics to a sum of random tallies. Section IX discusses how to apply batch statistics using MCNP6. Section X presents COSUBS, describing its command-line options and logic. Sections XI through XVI present numerical results for various test problems. Section XVII is a summary and conclusions. Appendix A derives the theoretical Monte Carlo tally variance given certain assumptions; these variances are used to verify the batch statistics for some of the problems. Appendix B lists the MCNP6 input for the unperturbed example problem. Appendix C presents modifications made to MCNP6.3 to support this work.

97 MATHEMATICS AND COMPUTING↗