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NASA NTRSDate not supplied

The Solar Clock

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C.T. Russell↗
NASA NTRS2012

Real-Time Distributed Embedded Oscillator Operating Frequency Monitoring

A document discusses the utilization of embedded clocks inside of operating network data links as an auxiliary clock source to satisfy local oscillator monitoring requirements. Modem network interfaces, typically serial network links, often contain embedded clocking information of very tight precision to recover data from the link. This embedded clocking data can be utilized by the receiving device to monitor the local oscillator for tolerance to required specifications, often important in high-integrity fault-tolerant applications. A device can utilize a received embedded clock to determine if the local or the remote device is out of tolerance by using a single link. The local device can determine if it is failing, assuming a single fault model, with two or more active links. Network fabric components, containing many operational links, can potentially determine faulty remote or local devices in the presence of multiple faults. Two methods of implementation are described. In one method, a recovered clock can be directly used to monitor the local clock as a direct replacement of an external local oscillator. This scheme is consistent with a general clock monitoring function whereby clock sources are clocking two counters and compared over a fixed interval of time. In another method, overflow/underflow conditions can be used to detect clock relationships for monitoring. These network interfaces often provide clock compensation circuitry to allow data to be transferred from the received (network) clock domain to the internal clock domain. This circuit could be modified to detect overflow/underflow conditions of the buffering required and report a fast or slow receive clock, respectively.

Pollock, Julie↗
NASA NTRSDate not supplied

Estimation of Timing Performance with Pulsed Laser Links for Small Satellite PNT

Satellite constellations are growing in size and in utility for applications as diverse as providing reliable, low-latency internet service to rural areas orEarth science missions.This expansion of satellite constellations brings attention to the need for responsive and reliable satellite communication.Current research in the PrecisionSpace Systems Laboratory at the University of Florida focuses on using pulsed laser communications as the method of relaying time signals instead of the radio frequency (RF)signals.The upcoming CLICK (CubeSat Laser Infrared CrosslinK) missions (Massachusetts Institute of Technology, University of Florida, NASA Ames Research Center) will demonstrate a spacecraft-to-spacecraft laser communication link and time-transfer.For pre-flight technology assessment of missions such as CLICK, a simulation of a spacecraft constellation in Earth orbit has been created to estimate clock synchronization and precision orbit determination based on measured instrumentation performance.We have developed a novel MATLAB-based numerical simulator to model spacecraft-to-spacecraft laser time-transfer and estimate the offset between the spacecraft clocks over time.This simulation includes timing errors associated with laser pulse generation and detection, as well as non-Gaussian clock drift models.The two on-board clocks modeled are a cesium-based Chip-Scale Atomic Clock (CSAC) and a rubidium-based Miniature Atomic Clock (MAC), both produced by Microchip.An example case of two spacecraft in a circular, low-Earth orbit receiving GPS position, GPS timing, and laser pulse time-of-flight measurements is simulated.The positions and velocities of the two spacecraft at a reference epoch and the constant clock model coefficients are estimated.Polynomial models of different orders were used as clock models. The effect of clock model order on the root-mean-square (RMS) of the clock error is apparent in the case using GPS and lasing measurements, showing that the clock model improves with increasing clock model order. Results compare the estimated clock model of a mission operation that only uses GPS measurements and a mission operation that uses both GPS and laser pulse time-of-flight measurements between spacecraft referenced to their on-board CSACs or on-board MACs. Including lasing measurements reduces the RMS clock model error by approximately 80% of the RMS of the cases with only GPS measurements.This simulation tool can be used to optimize the lasing operations schedule based on mission timing performance objectives. During this presentation, I will discuss the details of the simulation and clock model estimation, as well as discuss the results.I will compare the results of incorporating lasing timing measurements to using only GPS measurements and the outcomes of using different orders of polynomials.

Timing Performance↗
NASA NTRS2004

Eight-Channel Continuous Timer

A custom laboratory electronic timer circuit measures the durations of successive cycles of nominally highly stable input clock signals in as many as eight channels, for the purpose of statistically quantifying the small instabilities of these signals. The measurement data generated by this timer are sent to a personal computer running software that integrates the measurements to form a phase residual for each channel and uses the phase residuals to compute Allan variances for each channel. (The Allan variance is a standard statistical measure of instability of a clock signal.) Like other laboratory clock-cycle-measuring circuits, this timer utilizes an externally generated reference clock signal having a known frequency (100 MHz) much higher than the frequencies of the input clock signals (between 100 and 120 Hz). It counts the number of reference-clock cycles that occur between successive rising edges of each input clock signal of interest, thereby affording a measurement of the input clock-signal period to within the duration (10 ns) of one reference clock cycle. Unlike typical prior laboratory clock-cycle-measuring circuits, this timer does not skip some cycles of the input clock signals. The non-cycle-skipping feature is an important advantage because in applications that involve integration of measurements over long times for characterizing nominally highly stable clock signals, skipping cycles can degrade accuracy. The timer includes a field-programmable gate array that functions as a 20-bit counter running at the reference clock rate of 100 MHz. The timer also includes eight 20-bit latching circuits - one for each channel - at the output terminals of the counter. Each transition of an input signal from low to high causes the corresponding latching circuit to latch the count at that instant. Each such transition also sets a status flip-flop circuit to indicate the presence of the latched count. A microcontroller reads the values of all eight status flipflops and then reads the latched count for each channel for which the flip-flop indicates the presence of a count. Reading the count for each channel automatically causes the flipflop of that channel to be reset. The microcontroller places the counts in time order, identifies the channel number for each count, and transmits these data to the personal computer.

Cole, Steven↗
NASA NTRS1996

Common View Time Transfer Using Worldwide GPS and DMA Monitor Stations

Analysis of the on-orbit Navstar clocks and the Global Positioning System (GPS) monitor station reference clocks is performed by the Naval Research Laboratory using both broadcast and postprocessed precise ephemerides. The precise ephemerides are produced by the Defense Mapping Agency (DMA) for each of the GPS space vehicles from pseudo-range measurements collected at five GPS and at five DMA monitor stations spaced around the world. Recently, DMA established an additional site co-located with the US Naval Observatory precise time site. The time reference for the new DMA site is the DoD Master Clock. Now, for the first time, it is possible to transfer time every 15 minutes via common view from the DoD Master Clock to the 11 GPS and DMA monitor stations. The estimated precision of a single common-view time transfer measurement taken over a 15-minute interval was between 1.4 and 2.7 nanoseconds. Using the measurements from all Navstar space vehicles in common view during the 15-minute interval, typically 3-7 space vehicles, improved the estimate of the precision to between 0.65 and 1.13 nanoseconds. The mean phase error obtained from closure of the time transfer around the world using the 11 monitor stations and the 25 space vehicle clocks over a period of 4 months had a magnitude of 31 picoseconds. Analysis of the low noise time transfer from the DoD Master Clock to each of the monitor stations yields not only the bias in the time of the reference clock, but also focuses attention on structure in the behaviour of the reference clock not previously seen. Furthermore, the time transfer provides a a uniformly sampled database of 15-minute measurements that make possible, for the first time, the direct and exhaustive computation of the frequency stability of the monitor station reference clocks. To lend perspective to the analysis, a summary is given of the discontinuities in phase and frequency that occurred in the reference clock at the Master Control Station during the period covered by the analysis.

Reid, Wilson G.↗
NASA NTRS2004

A 2-to-48-MHz Phase-Locked Loop

A 2-to-48-MHz phase-locked loop (PLL), developed for the U.S. space program, meets or exceeds all space shuttle clock electrical interface requirements by taking as its reference a 2-to-48-MHz clock signal and outputting a phaselocked clock signal set at the same frequency as the reference clock with transistor- transistor logic (TTL) voltage levels. Because it is more adaptable than other PLLs, the new PLL can be used in industries that employ signaling devices and as a tool in future space missions. A conventional PLL consists of a phase/frequency detector, loop filter, and voltage-controlled oscillator in which each component exists individually and is integrated into a single device. PLL components phase-lock to a single frequency or to a narrow bandwidth of frequencies. It is this design, however, that prohibits them from maintaining phase lock to a dynamically changing reference clock when a large bandwidth is required a deficiency the new PLL overcomes. Since most PLL components require their voltage-controlled oscillators to operate at greater than 2-MHz frequencies, conventional PLLs often cannot achieve the low-frequency phase lock allowed by the new PLL. The 2-to-48-MHz PLL is built on a wire-wrap board with pins wired to three position jumpers; this makes changing configurations easy. It responds to variations in voltage-controlled oscillator (VCO) ranges, duty cycle, signal-to-noise ratio (SNR), amplitude, and jitter, exceeding design specifications. A consensus state machine, implemented in a VCO range detector which assures the PLL continues to operate in the correct range, is the primary control state machine for the 2-to-48-MHz PLL circuit. By using seven overlapping frequency ranges with hysteresis, the PLL output sets the resulting phase-locked clock signal at a frequency that agrees with the reference clock with TTL voltage levels. As a space-shuttle tool, the new PLL circuit takes the noisy, degraded reference clock signals as input and outputs phase-locked clock signals of the same frequency but with a corrected wave shape. Since its configuration circuit can be easily changed, the new PLL can do the following: readily respond to variations in VCO ranges, duty cycle, SNR, amplitude, and jitter; continuously operate in the correct VCO range because of its consensus state machine; and use its range detector implements to overlap seven frequency ranges with hysteresis, thus giving the current design a flexibility that exceeds anything available at the time of this development. These features will benefit any industry in which safe and timely clock signals are vital to operation.

Koudelka, Robert D.↗