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At least 559 records · Page 31

Modeling of a bubble-memory organization with self-checking translators to achieve high reliability.

Study of the design and modeling of a highly reliable bubble-memory system that has the capabilities of: (1) correcting a single 16-adjacent bit-group error resulting from failures in a single basic storage module (BSM), and (2) detecting with a probability greater than 0.99 any double errors resulting from failures in BSM's. The results of the study justify the design philosophy adopted of employing memory data encoding and a translator to correct single group errors and detect double group errors to enhance the overall system reliability.

Bouricius, W. G.↗

Shuttle orbiter Ku-band radar/communications system design evaluation. Ku band bent-pipe channel performance evaluation

Because of difficulties with the bit detector of the SPA mode 1 channel 3 input port, a new bit synchronizer was required. The two prime candidate designs are described and analyzed. The selected design is a modification of one which utilizes a phase frequency detector to track the received data clock frequency and a mid-bit transition point sample detector to generate a bit timing error (phase error) signal to control the relative phase between the local clock and the local data stream. The model used to calculate the effects of cable attenuation and rise time degradation is discussed.

Holmes, J. K.↗

An interferometer-based phase control system

A system for focusing and pointing the SPS power beam is discussed. The system is ground based and closed loop. One receiving antenna is required on earth. A conventional uplinked data channel transmits an 8-bit phase error correction back to the SPS for sequential calibration of each power module. Beam pointing resolution is better than 140 meters at the rectenna.

Ott, J. H.↗

An interferometer-based phase control system

A system for focusing and pointing the SPS power beam is discussed. The system is ground based and closed loop. One receiving antenna is required on Earth. A conventional uplink data channel transmits an 8-bit phase error correlation back to the SPS for sequential calibration of each power module. Beam pointing resolution is better than 140 meters at the Rectenna.

Ott, J. H.↗

An interferometer based phase control system

An interferometer based phase control system for focusing and pointing the solar power satellite (SPS) power beam is discussed. The system is ground based and closed loop. One receiving antenna is required on Earth. A conventional uplink data channel transmits an 8 bit phase error correction back to the SPS for sequential calibration of each power module. Beam pointing resolution is better than 140 meters at the rectenna.

Ott, J. H.↗

Adaptive Quantizer for Burst Synthetic-Aperture Radar

Adaptive quantizer for burst-mode synthetic-aperture radar reduces data rate of return signal. Device, called block floating-point quantizer (BFPQ) basically analog-to-digital converter that covers wide dynamic range and discards appropriate lower order bits. BFPQ is, in effect, digital approximator with automatic gain control. Moves floatingpoint marker binary representation of signal data in accordance with perceived dynamic range. Available step sizes thus limited to multiples of underlying smallest quantization step (represented by lowest order bit). Retains only first K most significant bits of signal; (L,K) BFPQ is one that does K-bit quantization of signal originally quantized to L bits. Quantization error simply difference between actual signal level and its binary approximation. Other potential applications for BFPQ include speech compression and picture data compression.

Joo, T. H.↗

Iterative demodulation and decoding of coded non-square QAM

Simulation results show that, with iterative demodulation and decoding, coded NS-8QAM performs 0.5 dB better than standard 8QAM and 0.7 dB better than 8PSK at BER= 10(sup -5), when the FEC code is the (15, 11) Hamming code concatenated with a rate-1 accumulator code, while coded NS-32QAM performs 0.25 dB better than standard 32QAM.

iterative decoding QAM bit error rate capacity↗

Programmatic Impact of SDRAM SEFI

The Elpida EDS5104(08)ABTA 512Mb SDRAM is examined for programmatic impact of SEE. Use cases for the devices including EDAC and mode register reload are examined. Results indicate some SEE mitigation methods require careful application to achieve system-level benefits, while some event types are essentially mitigated by the application use. In the studied devices MBE and SEFI are identified and investigated as mechanisms requiring special consideration.

Single Event Functionality Interrupt (SEFI)↗

Programmable Logic Device (PLD) Design Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. At the conclusion of the development, the software and hardware description language (HDL) code was delivered to JSC for their use in their iPAS test bed to get hands-on experience with the STRS standard, and for development of their own STRS Waveforms on the now STRS compliant platform.The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe the design of the HDL code for the FPGA portion of the iPAS STRS Radio particularly the design of the FPGA wrapper and the test waveform.

VHDL↗

Hardware Interface Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio Ssystem (STRS) Radio

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.

Flight Computer↗