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At least 559 records · Page 31

Operation of the ATLAS trigger system in Run 2

The ATLAS experiment at the Large Hadron Collider employs a two-level trigger system to record data at an average rate of 1 kHz from physics collisions, starting from an initial bunch crossing rate of 40 MHz. During the LHC Run 2 (2015–2018), the ATLAS trigger system operated successfully with excellent performance and flexibility by adapting to the various run conditions encountered and has been vital for the ATLAS Run-2 physics programme. For proton-proton running, approximately 1500 individual event selections were included in a trigger menu which specified the physics signatures and selection algorithms used for the data-taking, and the allocated event rate and bandwidth. The trigger menu must reflect the physics goals for a given data collection period, taking into account the instantaneous luminosity of the LHC and limitations from the ATLAS detector readout, online processing farm, and offline storage. This document discusses the operation of the ATLAS trigger system during the nominal proton-proton data collection in Run 2 with examples of special data-taking runs. Aspects of software validation, evolution of the trigger selection algorithms during Run 2, monitoring of the trigger system and data quality as well as trigger configuration are presented.

43 PARTICLE ACCELERATORS↗

Fast wave interferometer for ion density measurement on DIII-D

=A fast wave interferometer (FWI), which can measure ion mass density, has been developed on DIII-D for its use on future fusion reactors, as well as for the study of ion behavior in current plasma devices. The frequency of the fast waves used for the FWI is around 60 MHz, and require antennas and coaxial cables or waveguides, which, unlike traditional mirror-based optical interferometers, are less susceptible to neutron/gamma-ray radiation and are relatively immune to impurity deposition and erosion as well as alignment issues. The bulk ion density evaluated using FWI show good agreement with that derived from CO 2 interferometry within about 15%. When the ion mass density measurement by FWI is combined with an electron density measurement from CO 2 interferometry, Z eff measurements are also enabled and are in agreement with those from visible Bremsstrahlung measurements. Additionally, large-bandwidth FWI measurements clearly resolve 10–100 kHz coherent modes and demonstrate its potential as a core fluctuation diagnostic, sensitive to both magnetic and ion density perturbations.

Instruments & Instrumentation↗

The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC

The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10 –15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

Instruments & Instrumentation↗

Readout electronics for the CMS Phase II Endcap Calorimeter: system overview and prototyping experience

Abstract The frontend readout system for the silicon section of the CMS Phase II Endcap Calorimeter faces unique challenges due to the high channel count and associated bandwidth, limited physical space, as well as radiation tolerance requirements. I will give an overview of the frontend electronics design and will discuss the recent experience obtained from the first test system that integrates the HGCROC2 readout ASIC, lpGBT, and VTRX+ in a realistic manner, linking together prototypes of the hexaboard, engine, and wagon boards.

Instruments & Instrumentation↗

100 Gb/s High Throughput Serial Protocol (HTSP) for data acquisition systems with interleaved streaming

Demands on Field-Programmable Gate Array (FPGA) data transport have been increasing over the years as frame sizes and refresh rates increase. As the bandwidths requirements increase the ability to implement data transport protocol layers using "soft" programmable logic becomes harder and start to require harden IP blocks implementation. To reduce the number of physical links and interconnects, it is common for data acquisition systems to require interleaving of streams on the same link (e.g. streaming data and streaming register access). Further, this paper presents a way to leverage existing FPGA harden IP blocks to achieve a robust, low latency 100 Gb/s point-to-point link with minimal programmable logic overhead geared towards the needs of data acquisition systems with interleaved streaming requirements.

47 OTHER INSTRUMENTATION↗

Electronics for the far-forward CMS muon detector upgrade, ME0

Abstract With the High Luminosity upgrade of the Large Hadron Collider (LHC) we expect increased instantaneous luminosities up to 7.5 × 10 34 cm −2 s −1 , or five times more than the original values. In order to maintain performance of the Compact Muon Solenoid (CMS) experiment under these conditions, ME0 is one of three new muon sub-detectors being added, along with GE1/1 and GE2/1, which use the triple Gas Electron Multiplier (GEM) technology. ME0 is designed to cover the forward region of 2.0 < | η | < 2.8, thus improving muon reconstruction at high background rates by supplementing other overlapping muon subsystems up to | η | = 2.4, while also extending the acceptance for the first time to | η | = 2.8. The readout electronics for ME0 must be designed to accommodate high data rates and be sufficiently radiation hard to operate close to the beamline. The Optohybrid (OH) board for ME0, which reads out data from the front-end VFAT3b ASICs, has therefore been designed to operate without an FPGA (unlike GE1/1 and GE2/1) to ensure radiation hardness. The ME0 OH uses the radiation-hard CERN-designed lpGBT ASIC and VTRx+ optical transceiver module for high bandwidth optical links up to 10.24 Gb/s. The backend system is based on the ATCA standard. The design and development status of the readout electronics for ME0 is presented, along with recent results from integration tests performed using the first prototypes.

Instruments & Instrumentation↗

Synchrotron light source X-ray detection with Low-Gain Avalanche Diodes

Abstract Low Gain Avalanche Diodes (LGADs) represent the state-of-the-art in timing measurements and will instrument the future Timing Detectors of ATLAS and CMS for the High-Luminosity LHC. While initially conceived as a sensor for charged particles, the intrinsic gain of LGADs makes it possible to detect low-energy X-rays with good energy resolution and excellent time resolution (tens of picoseconds). Using the Stanford Synchrotron Radiation Lightsource (SSRL) at SLAC, several LGADs designs were characterized with energies from 5 to 70 keV. The SSRL provides 10 ps pulsed X-ray bunches separated by 2 ns intervals with an energy dispersion (ΔE/E) of 10 -4 . LGADs from Hamamatsu Photonics (HPK) and Brookhaven National Laboratory (BNL) with different thicknesses ranging from 20 μm to 50 μm and different gain layer designs were read out using fast amplification boards and digitized with a high bandwidth and high sampling rate oscilloscope. PIN devices from HPK and AC-LGADs from BNL were characterized as well. A systematic and detailed characterization of the devices' energy linearity, resolution, and time resolution as a function of X-ray energy was performed for different biasing voltages at room temperature and are reported in this work. The charge collection and multiplication mechanism were simulated using Geant4 and TCAD Sentaurus, providing an important handle for interpreting the data.

Instruments & Instrumentation↗

A demonstrator for a real-time AI-FPGA-based triggering system for sPHENIX at RHIC

The RHIC interaction rate at sPHENIX will reach around 3 MHz in pp collisions and requires the detector readout to reject events by a factor of over 200 to fit the DAQ bandwidth of 15 kHz. Some critical measurements, such as heavy flavor production in pp collisions, often require the analysis of particles produced at low momentum. This prohibits adopting the traditional approach, where data rates are reduced through triggering on rare high momentum probes. We explore a new approach based on real-time AI technology, adopt an FPGA-based implementation using a custom designed FELIX-712 board with the Xilinx Kintex Ultrascale FPGA, and deploy the system in the detector readout electronics loop for real-time trigger decision.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Integration of EDWARD readout architecture in full-field fluorescence imaging detector

Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD ( E vent- D riven W ith A ccess and R eset D ecoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one, named 3FI65P1, is a full device with the analog pixel circuitry suited for full-field fluorescence imaging. It is already manufactured, and preliminary results are presented. Finally, the second chip, named EDWARD65P1, contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of the EDWARD architecture alone.

47 OTHER INSTRUMENTATION↗

The 140 GHz notch filter development for millimeter-wave diagnostics protection on the stellarator Wendelstein 7-X

The notch filter plays a crucial role as a protective component in microwave diagnostics, primarily by addressing issues related to catastrophic interference. Designed for millimeter-wave diagnostics on the stellarator Wendelstein 7-X (W7-X), a WR-6 waveguide-based notch filter has been successfully developed to effectively isolate leakage from auxiliary heating gyrotrons operating at 140 GHz. The filter incorporates cylindrical cavities resonating at 140 GHz for the TE11p mode, with coupling structures that are designed and optimized for high-efficiency coupling. This configuration simplifies fabrication, thereby ensuring high-yield production. Experimental fabrication and in-house characterization confirm the notch filter's exceptional performance, with over 60 dB rejection in the vicinity of 140 GHz and low insertion loss (< 2 dB) above and below the notch frequency across a broad frequency bandwidth (121–138 GHz, 142–163 GHz). Furthermore, the utilization of this high-frequency structure fabrication technology can be applied to millimeter-wave diagnostics on other machines. In addition to the design elements of the notch filter, this paper also provides a detailed discussion of the fabrication process and methodology.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing↗

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗

Large-scale real-time signal processing in physics experiments: the ALICE TPC FPGA pipeline

For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.

Digital signal processing (DSP)↗

Ultrafast adiabatic frequency conversion

Abstract Ultrafast adiabatic frequency conversion is a powerful method, capable of efficiently and coherently transfering ultrashort pulses between different spectral ranges, e.g. from near-infrared to mid-infrared, visible or ultra-violet. This is highly desirable in research fields that are currently limited by available ultrafast laser sources, e.g. attosecond science, strong-field physics, high-harmonic generation spectroscopy and multidimensional mid-infrared spectroscopy. Over the past decade, adiabatic frequency conversion has substantially evolved. Initially applied to quasi-monochromatic, undepleted pump interactions, it has been generalized to include ultrashort, broadband, fully-nonlinear dynamics. Through significant theoretical development and experimental demonstrations, it has delivered new capabilities and superior performance in terms of bandwidth, efficiency and robustness, as compared to other frequency conversion techniques. This article introduces the concept of adiabatic nonlinear frequency conversion, reviews its theoretical foundations, presents significant milestones and highlights contemporary ultrafast applications that may, or already do, benefit from utilizing this method.

Margules, Peleg (ORCID:0000000335573370)↗

Dispersion-engineered χ(2) nanophotonics: a flexible tool for nonclassical light

Abstract This article reviews recent progress in quasi-phasematched χ ( 2 ) nonlinear nanophotonics, with a particular focus on dispersion-engineered nonlinear interactions. Throughout this article, we establish design rules for the bandwidth and interaction lengths of various nonlinear processes, and provide examples for how these processes can be engineered in nanophotonic devices. In particular, we apply these rules towards the design of sources of non-classical light and show that dispersion-engineered devices can outperform their conventional counterparts. Examples include ultra-broadband optical parametric amplification as a resource for measurement-based quantum computation, dispersion-engineered spontaneous parametric downconversion as a source of separable biphotons, and synchronously pumped nonlinear resonators as a potential route towards single-photon nonlinearities.

Jankowski, Marc (ORCID:0000000318457415)↗

Passive radiative thermal management using phase-change metasurfaces

Abstract Realizing innovative composite materials with passive thermal management capabilities and minimal ecological footprints is a challenging but much sought-after goal that would have a transformative effect on renewable energy sciences. We demonstrate an environmentally friendly metasurface utilizing vanadium dioxide (VO 2 ) that offers responsiveness to ambient temperature and potentially long-term stability. The metasurface enables passive thermal management by self-adjusting its absorptivity and emissivity response over a broad bandwidth ranging from visible to mid-infrared (IR) wavelengths. Above the VO 2 phase transition the metasurface exhibits increased mid-IR emissivity and reduced visible/near-IR absorptivity, creating an efficient radiative emission channel in the first atmospheric transparency window with reduced absorption of solar radiation. In contrast, below VO 2 ’s transition temperature, the metasurface increasingly absorbs sun light while minimizing mid-IR radiative heat losses. Moreover, a functional silicon layer eliminates the need for an additional capping layer commonly employed to protect VO 2 from environmental degradation. The additional protective layer often impedes the use and performance of VO 2 based devices in terrestrial as well as spacecraft applications. Therefore, the proposed durable and eco-friendly metasurface will be an excellent candidate for essential passive thermal regulation systems across residential and terrestrial applications.

42 ENGINEERING↗

Accelerating data acquisition with FPGA-based edge machine learning: a case study with LCLS-II

New scientific experiments and instruments generate vast amounts of data that need to be transferred for storage or further processing, often overwhelming traditional systems. Edge machine learning (EdgeML) addresses this challenge by integrating machine learning (ML) algorithms with edge computing, enabling real-time data processing directly at the point of data generation. EdgeML is particularly beneficial for environments where immediate decisions are required, or where bandwidth and storage are limited. In this paper, we demonstrate a high-speed configurable ML model in a fully customizable EdgeML system using a field programmable gate array (FPGA). Our demonstration focuses on an angular array of electron spectrometers, referred to as the ‘CookieBox,’ developed for the Linac Coherent Light Source II project. The EdgeML system captures 51.2 Gbps from a 6.4 GS s −1 analog to digital converter and is designed to integrate data pre-processing and ML inside an FPGA. Our implementation achieves an inference latency of 0.2 µs for the ML model, and a total latency of 0.4 µs for the complete EdgeML system, which includes pre-processing, data transmission, digitization, and ML inference. The modular design of the system allows it to be adapted for other instrumentation applications requiring low-latency data processing.

97 MATHEMATICS AND COMPUTING↗

Towards a self-driving trigger at the LHC: adaptive response in real time

Real-time data filtering and selection—or trigger—systems at high-throughput scientific facilities such as the experiments at the Large Hadron Collider must process extremely high-rate data streams under stringent bandwidth, latency, and storage constraints. Yet these systems are typically designed as static, hand-tuned menus of selection criteria grounded in prior knowledge and simulation. In this work, we further explore the concept of a self-driving trigger, an autonomous data-filtering framework that reallocates resources and adjusts thresholds dynamically in real-time to optimize signal efficiency, rate stability, and computational cost as instrumentation and environmental conditions evolve. We introduce a benchmark ecosystem to emulate realistic collider scenarios and demonstrate real-time optimization of a menu including canonical energy sum triggers as well as modern anomaly-detection algorithms that target non-standard event topologies using machine learning. Using simulated data streams and publicly available collision data from the Compact Muon Solenoid experiment, we demonstrate the capability to dynamically and automatically optimize trigger performance under specific cost objectives without manual retuning. Our adaptive strategy shifts trigger design from static menus with heuristic tuning to intelligent, automated, data-driven control, unlocking greater flexibility and discovery potential in future high-energy physics analyses.

Emami, Shaghayegh [Michigan U.] (ORCID:00090007589↗