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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 559 records · Page 31
All sourcesNASA NTRSDOE OSTI
DOE OSTI2013

Improving chemical vapor deposition graphene conductivity using molybdenum trioxide: An in-situ field effect transistor study

By using in situ field effect transistor characterization integrated with molecular beam epitaxy technique, we demonstrate the strong surface transfer p-type doping effect of single layer chemical vapor deposition (CVD) graphene, through the surface functionalization of molybdenum trioxide (MoO{sub 3}) layer. After doping, both the hole and electron mobility of CVD graphene are nearly retained, resulting in significant enhancement of graphene conductivity. With coating of 10 nm MoO{sub 3}, the conductivity of CVD graphene can be increased by about 7 times, showing promising application for graphene based electronics and transparent, conducting, and flexible electrodes.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2014

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2014

High performance organic field-effect transistors with ultra-thin HfO{sub 2} gate insulator deposited directly onto the organic semiconductor

We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO{sub 2} gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm{sup 2}/V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO{sub 2} layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Molecular doping for control of gate bias stress in organic thin film transistors

The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Palladium nanoparticle decorated silicon nanowire field-effect transistor with side-gates for hydrogen gas detection

A silicon nanowire field-effect transistor (SiNW FET) with local side-gates and Pd surface decoration is demonstrated for hydrogen (H{sub 2}) detection. The SiNW FETs are fabricated by top-down method and functionalized with palladium nanoparticles (PdNPs) through electron beam evaporation for H{sub 2} detection. The drain current of the PdNP-decorated device reversibly responds to H{sub 2} at different concentrations. The local side-gates allow individual addressing of each sensor and enhance the sensitivity by adjusting the working region to the subthreshold regime. A control experiment using a non-functionalized device verifies that the hydrogen-sensitivity is originated from the PdNPs functionalized on the SiNW surface.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2014

Adjustment of threshold voltage in AlN/AlGaN/GaN high-electron mobility transistors by plasma oxidation and Al{sub 2}O{sub 3} atomic layer deposition overgrowth

We discuss possibilities of adjustment of a threshold voltage V{sub T} in normally off GaN high-electron mobility transistors (HEMTs) without compromising a maximal drain current I{sub DSmax}. Techniques of a low power plasma or thermal oxidation of 2-nm thick AlN cap over 3-nm thick AlGaN barrier are developed and calibrated for a thorough oxidation of the cap with a minimal density of surface donors at the inherent oxide-semiconductor interface. It has been shown that while a thermal oxidation technique leads to the channel and/or interface degradation, low density of surface donors and scalability of V{sub T} with additionally overgrown Al{sub 2}O{sub 3} may be obtained for plasma oxidized HEMTs. With 10-nm thick Al{sub 2}O{sub 3} deposited at 100 °C by atomic-layer deposition, we obtained V{sub T} of 1.6 V and I{sub DSmax} of 0.48 A/mm at a gate voltage of V{sub GS} = 8 V. Density of surface donors was estimated to be about 1.2 × 10{sup 13} cm{sup −2}, leaving most of the negative polarization charge at the semiconductor surface uncompensated. Further reduction of surface donors may be needed for even higher V{sub T}.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Design, fabrication, and analysis of p-channel arsenide/antimonide hetero-junction tunnel transistors

In this paper, we demonstrate InAs/GaSb hetero-junction (hetJ) and GaSb homo-junction (homJ) p-channel tunneling field effect transistors (pTFET) employing a low temperature atomic layer deposited high-κ gate dielectric. HetJ pTFET exhibited drive current of 35 μA/μm in comparison to homJ pTFET, which exhibited drive current of 0.3 μA/μm at V{sub DS} = −0.5 V under DC biasing conditions. Additionally, with pulsing of 1 μs gate voltage, hetJ pTFET exhibited enhanced drive current of 85 μA/μm at V{sub DS} = −0.5 V, which is the highest reported in the category of III-V pTFET. Detailed device characterization was performed through analysis of the capacitance-voltage characteristics, pulsed current-voltage characteristics, and x-ray diffraction studies.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

High-performance, low-operating voltage, and solution-processable organic field-effect transistor with silk fibroin as the gate dielectric

We report the use of silk fibroin as the gate dielectric material in solution-processed organic field-effect transistors (OFETs) with poly(3-hexylthiophene) (P3HT) as the semiconducting layer. Such OFETs exhibit a low threshold of −0.77 V and a low-operating voltage (0 to −3 V) compatible with the voltage level commonly-used in current electronic industry. The carrier mobility of such OFETs is as high as 0.21 cm{sup 2} V{sup −1} s{sup −1} in the saturation regime, comparable to the best value of P3HT-based OFETs with dielectric layer that is not solution-processed. The high-performance of this kind of OFET is related with the high content of β strands in fibroin dielectric which leads to an array of fibers in a highly ordered structure, thus reducing the trapping sites at the semiconductor/dielectric interface.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Fermi-level shifts in graphene transistors with dual-cut channels scraped by atomic force microscope tips

We investigate the electronic properties of p-type graphene transistors on silicon dioxide with dual-cut channels that were scraped using atomic force microscope tips. In these devices, the current is forced to squeeze into the path between the two cuts rather than flow directly through the graphene sheet. We observe that the gate voltages with minimum current shift toward zero bias as the sizes of the dual-cut regions increase. These phenomena suggest that the Fermi levels in the dual-cut regions are shifted toward the Dirac points after the mechanical scraping process.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Thickness dependent low-frequency noise characteristics of a-InZnO thin-film transistors under light illumination

The influence of illumination on the electrical characteristics of amorphous indium–zinc oxide (a-IZO) thin-film transistors (TFTs) has been investigated. The electrical properties are found to depend significantly on the active thickness (T{sub IZO}) of the a-IZO TFT. The active thickness is seen to play a major role in the carrier transport mechanism. Based on the carrier fluctuation model, the low-frequency noise (LFN) characteristics of a-IZO devices of varying thicknesses were evaluated before as well as after illumination. Similar to the results of DC and capacitance–voltage (C–V) measurements, the LFN characteristics too show that the light-induced carrier transport becomes significantly enhanced for relatively thick (T{sub IZO} ≥ 60 nm) a-IZO devices.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Coplanar amorphous-indium-gallium-zinc-oxide thin film transistor with He plasma treated heavily doped layer

We report thermally stable coplanar amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with heavily doped n{sup +} a-IGZO source/drain regions. Doping is through He plasma treatment in which the resistivity of the a-IGZO decreases from 2.98 Ω cm to 2.79 × 10{sup −3} Ω cm after treatment, and then it increases to 7.92 × 10{sup −2} Ω cm after annealing at 300 °C. From the analysis of X-ray photoelectron spectroscopy, the concentration of oxygen vacancies in He plasma treated n{sup +}a-IGZO does not change much after thermal annealing at 300 °C, indicating thermally stable n{sup +} a-IGZO, even for TFTs with channel length L = 4 μm. Field-effect mobility of the coplanar a-IGZO TFTs with He plasma treatment changes from 10.7 to 9.2 cm{sup 2}/V s after annealing at 300 °C, but the performance of the a-IGZO TFT with Ar or H{sub 2} plasma treatment degrades significantly after 300 °C annealing.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Lateral carrier diffusion and current gain in terahertz InGaAs/InP double-heterojunction bipolar transistors

The DC current gain in In{sub 0.53}Ga{sub 0.47}As/InP double-heterojunction bipolar transistors is computed based on a drift-diffusion model, and is compared with experimental data. Even in the absence of other scaling effects, lateral diffusion of electrons to the base Ohmic contacts causes a rapid reduction in DC current gain as the emitter junction width and emitter-base contact spacing are reduced. The simulation and experimental data are compared in order to examine the effect of carrier lateral diffusion on current gain. The impact on current gain due to device scaling and approaches to increase current gain are discussed.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Significant electrical control of amorphous oxide thin film transistors by an ultrathin Ti surface polarity modifier

We demonstrate an enhanced electrical stability through a Ti oxide (TiO{sub x}) layer on the amorphous InGaZnO (a-IGZO) back-channel; this layer acts as a surface polarity modifier. Ultrathin Ti deposited on the a-IGZO existed as a TiO{sub x} thin film, resulting in oxygen cross-binding with a-IGZO surface. The electrical properties of a-IGZO thin film transistors (TFTs) with TiO{sub x} depend on the surface polarity change and electronic band structure evolution. This result indicates that TiO{sub x} on the back-channel serves as not only a passivation layer protecting the channel from ambient molecules or process variables but also a control layer of TFT device parameters.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10{sup 5}, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10{sup 4} s.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

The behavior of off-state stress-induced electrons trapped at the buffer layer in AlGaN/GaN heterostructure field effect transistors

A measurement methodology involving the synchronous switching of gate to source voltage and drain to source voltage (V{sub DS}) was proposed for determining the shift of threshold voltage after an AlGaN/GaN heterostructure transistor endures high V{sub DS} off-state stress. The measurement results indicated slow electron detrapping behavior. The trap level was determined as (E{sub C} – 0.6 eV). Simulation tool was used to analyze the measurement results. The simulation results were consistent with the experimental results; and a relationship between the buffer trap and threshold voltage shift over time was observed.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Tensile strained Ge tunnel field-effect transistors: k · p material modeling and numerical device simulation

Group IV based tunnel field-effect transistors generally show lower on-current than III-V based devices because of the weaker phonon-assisted tunneling transitions in the group IV indirect bandgap materials. Direct tunneling in Ge, however, can be enhanced by strain engineering. In this work, we use a 30-band k · p method to calculate the band structure of biaxial tensile strained Ge and then extract the bandgaps and effective masses at Γ and L symmetry points in k-space, from which the parameters for the direct and indirect band-to-band tunneling (BTBT) models are determined. While transitions from the heavy and light hole valence bands to the conduction band edge at the L point are always bridged by phonon scattering, we highlight a new finding that only the light-hole-like valence band is strongly coupling to the conduction band at the Γ point even in the presence of strain based on the 30-band k · p analysis. By utilizing a Technology Computer Aided Design simulator equipped with the calculated band-to-band tunneling BTBT models, the electrical characteristics of tensile strained Ge point and line tunneling devices are self-consistently computed considering multiple dynamic nonlocal tunnel paths. The influence of field-induced quantum confinement on the tunneling onset is included. Our simulation predicts that an on-current up to 160 (260) μA/μm can be achieved along with on/off ratio > 10{sup 6} for V{sub DD} = 0.5 V by the n-type (p-type) line tunneling device made of 2.5% biaxial tensile strained Ge.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Growth parameter optimization and interface treatment for enhanced electron mobility in heavily strained GaInAs/AlInAs high electron mobility transistor structures

The optimization of heavily strained Ga{sub 0.25}In{sub 0.75}As/Al{sub 0.48}In{sub 0.52}As high electron mobility transistor structures is discussed in detail. The growth parameters and the channel layer interfaces were optimized in order to maximize the mobility of the two-dimensional electron gas. Structures composed of an 11 nm thick channel layer and a 4 nm thick spacer layer exhibited electron mobilities as high as 15 100 cm{sup 2}/Vs and 70 000 cm{sup 2}/Vs at 300 and 77 K, respectively, for channels including InAs strained layers. The sheet carrier density was kept above 2.5 × 10{sup 12} cm{sup −2} throughout the entire study.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

High-frequency characterization of thermionic charge transport in silicon-on-insulator nanowire transistors

We report on DC and microwave electrical transport measurements in silicon-on-insulator nano-transistors at low and room temperature. At low source-drain voltage, the DC current and radio frequency response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature are accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗