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At least 559 records · Page 31
All sourcesNASA NTRSDOE OSTI
NASA NTRS2013

Apparatus and Method for Compensating for Process, Voltage, and Temperature Variation of the Time Delay of a Digital Delay Line

A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Seefeldt, James↗
NASA NTRS1992

A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.

Fouts, Douglas J.↗
NASA NTRS2009

Number Codes Readable by Magnetic-Field-Response Recorders

A method of encoding and reading numbers incorporates some of the features of conventional optical bar coding and radio-frequency identification (RFID) tagging, but overcomes some of the disadvantages of both: (1) Unlike in conventional optical bar coding, numbers can be read without having a line of sight to a tag; and (2) the tag circuitry is simpler than the circuitry used in conventional RFID. The method is based largely on the principles described in Magnetic-Field-Response Measurement-Acquisition System (LAR-16908), NASA Tech Briefs, Vol. 30, No. 6 (June 2006) page 28. To recapitulate: A noncontact system includes a monitoring unit that acquires measurements from sensors at distances of the order of several meters. Each sensor is a passive radio-frequency (RF) resonant circuit in the form of one or more inductor(s) and capacitor(s). The monitoring unit a handheld unit denoted a magnetic field response recorder (MFRR) generates an RF magnetic field that excites oscillations in the resonant circuits resulting in the sensors responding with their own radiated magnetic field. The resonance frequency of each sensor is made to differ significantly from that of the other sensors to facilitate distinction among the responses of different sensors. The MFRR measures selected aspects of the sensor responses: in a typical application, the sensors are designed so that their resonance frequencies vary somewhat with the sensed physical quantities and, accordingly, the MFRR measures the resonance frequencies and variations thereof as indications of those quantities. In the present method, the resonance circuits are not used as sensors. Instead, the circuits are made to resonate at fixed frequencies that correspond to digits to be encoded. The number-encoding scheme is best explained by means of examples in which each resonant circuit consists of a spiral trace inductor electrically connected to a set of parallel-connected capacitors in the form of interdigitated electrode pairs (see figure). The inductor and capacitor(s) in each resonant circuit can be fabricated as a patterned thin metal film by means of established metal-deposition and -patterning techniques. The capacitance and, hence, the resonance frequency, depends on the number of interdigitated electrodes connected to the inductor. In a similar manner, sets of electrodes could be used.

Woodard, Stanley E.↗
NASA NTRS2004

Ultralow-Power Digital Correlator for Microwave Polarimetry

A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the autocorrelations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two intermediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2(exp 8) cycles of the sampling clock, up to a maximum of 2(exp 24) cycles. The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2(exp 8) the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over.

Piepmeier, Jeffrey R.↗
NASA NTRS2000

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Fossum, Eric R.↗
NASA NTRS2003

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Fossum, Eric R.↗
NASA NTRS1973

Digital single-sideband mixer.

Description of a simple single-sideband (SSB) mixer design that yields either a sum-frequency output with the difference-frequency output suppressed or vice-versa, and uses only 'digital' logic devices and no reactive or frequency-selective 'analog' (linear) circuit elements. A pair of outputs is generated in phase quadrature. It is shown that SSB frequency conversion can be accomplished for many applications much more efficiently with simple digital circuitry than in the usual way with complicated linear frequency selective filter and phasing circuits.

Counselman, C. C., III↗
NASA NTRS1984

Test structures for propagation delay measurements on high-speed integrated circuits

The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.

Long, S. I.↗
NASA NTRS1984

Detection of Floating Inputs in Logic Circuits

Simple modification of oscilloscope probe allows easy detection of floating inputs or tristate outputs in digital-IC's. Oscilloscope probe easily modified with 1/4 W resistor and switch for detecting floating inputs in CMOS logic circuits.

Cash, B.↗
DOE OSTI2022

Small-world complex network generation on a digital quantum processor

Abstract Quantum cellular automata (QCA) evolve qubits in a quantum circuit depending only on the states of their neighborhoods and model how rich physical complexity can emerge from a simple set of underlying dynamical rules. The inability of classical computers to simulate large quantum systems hinders the elucidation of quantum cellular automata, but quantum computers offer an ideal simulation platform. Here, we experimentally realize QCA on a digital quantum processor, simulating a one-dimensional Goldilocks rule on chains of up to 23 superconducting qubits. We calculate calibrated and error-mitigated population dynamics and complex network measures, which indicate the formation of small-world mutual information networks. These networks decohere at fixed circuit depth independent of system size, the largest of which corresponding to 1,056 two-qubit gates. Such computations may enable the employment of QCA in applications like the simulation of strongly-correlated matter or beyond-classical computational demonstrations.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2006

Digital Front End for Wide-Band VLBI Science Receiver

An upgrade to the very-long-baseline-interferometry (VLBI) science receiver (VSR) a radio receiver used in NASA's Deep Space Network (DSN) is currently being implemented. The current VSR samples standard DSN intermediate- frequency (IF) signals at 256 MHz and after digital down-conversion records data from up to four 16-MHz baseband channels. Currently, IF signals are limited to the 265-to-375-MHz range, and recording rates are limited to less than 80 Mbps. The new digital front end, denoted the Wideband VSR, provides improvements to enable the receiver to process wider bandwidth signals and accommodate more data channels for recording. The Wideband VSR utilizes state-of-the-art commercial analog-to-digital converter and field-programmable gate array (FPGA) integrated circuits, and fiber-optic connections in a custom architecture. It accepts IF signals from 100 to 600 MHz, sampling the signal at 1.28 GHz. The sample data are sent to a digital processing module, using a fiber-optic link for isolation. The digital processing module includes boards designed around an Advanced Telecom Computing Architecture (ATCA) industry-standard backplane. Digital signal processing implemented in FPGAs down-convert the data signals in up to 16 baseband channels with programmable bandwidths from 1 kHz to 16 MHz. Baseband samples are transmitted to a computer via multiple Ethernet connections allowing recording to disk at rates of up to 1 Gbps.

Jongeling, Andre↗
DOE OSTI2023

A 32-channels readout ASIC for X-ray spectrometry and tracking in the GAPS experiment

Here this work describes the architecture and the experimental results from the characterization of a 32-channels mixed-signal Application-Specific Integrated Circuit (ASIC) developed for the readout of the lithium-drifted silicon, Si(Li), detectors of the General AntiParticle Spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full custom integrated circuit, named SLIDER32 (32-channels Si-LI DEtector Readout) ASIC, has been produced in a commercial 180 nm CMOS technology. The ASIC is comprised of 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit SAR ADC and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in the paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1986

Steady-state probability density function of the phase error for a DPLL with an integrate-and-dump device

The steady-state behavior of a particular type of digital phase-locked loop (DPLL) with an integrate-and-dump circuit following the phase detector is characterized in terms of the probability density function (pdf) of the phase error in the loop. Although the loop is entirely digital from an implementation standpoint, it operates at two extremely different sampling rates. In particular, the combination of a phase detector and an integrate-and-dump circuit operates at a very high rate whereas the loop update rate is very slow by comparison. Because of this dichotomy, the loop can be analyzed by hybrid analog/digital (s/z domain) techniques. The loop is modeled in such a general fashion that previous analyses of the Real-Time Combiner (RTC), Subcarrier Demodulator Assembly (SDA), and Symbol Synchronization Assembly (SSA) fall out as special cases.

Simon, M.↗
NASA NTRS2003

Advanced Data Acquisition Systems

Current and future requirements of the aerospace sensors and transducers field make it necessary for the design and development of new data acquisition devices and instrumentation systems. New designs are sought to incorporate self-health, self-calibrating, self-repair capabilities, allowing greater measurement reliability and extended calibration cycles. With the addition of power management schemes, state-of-the-art data acquisition systems allow data to be processed and presented to the users with increased efficiency and accuracy. The design architecture presented in this paper displays an innovative approach to data acquisition systems. The design incorporates: electronic health self-check, device/system self-calibration, electronics and function self-repair, failure detection and prediction, and power management (reduced power consumption). These requirements are driven by the aerospace industry need to reduce operations and maintenance costs, to accelerate processing time and to provide reliable hardware with minimum costs. The project's design architecture incorporates some commercially available components identified during the market research investigation like: Field Programmable Gate Arrays (FPGA) Programmable Analog Integrated Circuits (PAC IC) and Field Programmable Analog Arrays (FPAA); Digital Signal Processing (DSP) electronic/system control and investigation of specific characteristics found in technologies like: Electronic Component Mean Time Between Failure (MTBF); and Radiation Hardened Component Availability. There are three main sections discussed in the design architecture presented in this document. They are the following: (a) Analog Signal Module Section, (b) Digital Signal/Control Module Section and (c) Power Management Module Section. These sections are discussed in detail in the following pages. This approach to data acquisition systems has resulted in the assignment of patent rights to Kennedy Space Center under U.S. patent # 6,462,684. Furthermore, NASA KSC commercialization office has issued licensing rights to Circuit Avenue Netrepreneurs, LLC , a minority-owned business founded in 1999 located in Camden, NJ.

Perotti, J.↗
NASA NTRS2014

All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Shuler, Robert L., Jr.↗
NASA NTRS2014

ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Schuler, Robert L., Jr.↗
NASA NTRS1995

CMOS Image Sensors: Electronic Camera On A Chip

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Space Microelectronics Image Sensors APS Digital I↗
DOE OSTI2025

Signal propagation in reversible digital mechanics

Digital mechanics explores information processing through binary, mechanical circuits. This work demonstrates a flexural, mechanical integrated circuit (m-IC) that achieves reversible, non-reciprocal signal propagation through integrated AND logic and memory. Our approach exploits sequential bistable transitions with symmetric energy wells, tunable stiffness, impedance matching, and AND gate non-linearity, to enable signal propagation, repeatability, and reversibility. We present a generalized model of logic kinematics and energetics, validated experimentally, to study energy flows, quantify energetic limits, and identify operating regimes for reversible logic. Macro-scale experiments confirm propagation dynamics, and new fabrication methods extend the architecture to micro-scale devices. By achieving controlled, reversible signal transmission across interconnected logic and memory, this work establishes a scalable platform for robust mechanical computing and adaptive sensing.

Johnson, Hilary A. [Lawrence Livermore National La↗