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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
DOE OSTI2014

Three-terminal resistive switching memory in a transparent vertical-configuration device

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Quantum dot based memory devices: Current status and future prospect by simulation perspective

We discuss the simulation of floating gate MOSFET memory performance consists of Si/Ge/Si quantum dots for electronics storage nodes with higk-κ material as the tunnel oxide. Heterostructure quantum dot was proposed to maintain the good memory performance without losing the long retention characteristic. As the results, retention time could be increase significantly without deteriorating the writing/erasing speed. By selected the dot size of 9–15nm and the tunnel oxide thickness of 2nm, the retention characteristic can reach up to 10{sup 9}s while the writing and erasing time at the order of 10{sup −6}s. By replace the SiO{sub 2} tunnel oxide with high-κ material such as HfO{sub 2}, ZrO{sub 2}, and Y{sub 2}O{sub 3} the leakage current due to the shrinkage of tunnel oxide thickness can be suppressed by the factor of 10 for the EOT lower than ∼1nm. Moreover, the charge-trapping that generated by the defect at Si substrate and higk-κ material interface are fully considered. We found that, the charge-trapping affects the retention time and memory operation performance. By increasing the charge-trapping depth and width, the memory operation time decrease significantly while the retention characteristic slightly improved.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Static critical phenomena in Co-Ni-Ga ferromagnetic shape memory alloy

Ferromagnetic shape memory alloys are smart materials because they exhibit temperature driven shape memory effect and magnetic field induced strain. Thus two types of energy, i.e. thermal and magnetic, are used to control their shape memory behaviour. Study of critical phenomenon in such materials has received increased experimental and theoretical attention for better understanding of the magnetic phase transition behavior as well as further development of ferromagnetic shape memory materials. In the present study we report the preparation and characterization of bulk Co{sub 45}Ni{sub 25}Ga{sub 30} alloy, prepared by a sequence of arc melting technique followed by homogenization at 1150 °C for 24 hours and ice-water quenching. Structural and magnetic properties of the alloys were studied by means of X-ray diffraction and vibrating sample magnetometer in an applied field range of ±18 kOe equipped with a high temperature oven. We have determined the critical temperature T{sub C} (∼375.5 K) and the critical exponents viz; β=0.40, γ=1.68 and δ=5.2. Asymptotic critical exponents β, γ, and δ obey Widom scaling relation, γ+β=βδ, and the magnetization data satisfy the scaling equation of state for second-order phase transition in the asymptotic critical region.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Fabrication of poly(methyl methacrylate)-MoS{sub 2}/graphene heterostructure for memory device application

Combination of two dimensional graphene and semi-conducting molybdenum disulfide (MoS{sub 2}) is of great interest for various electronic device applications. Here, we demonstrate fabrication of a hybridized structure with the chemical vapor deposited graphene and MoS{sub 2} crystals to configure a memory device. Elongated hexagonal and rhombus shaped MoS{sub 2} crystals are synthesized by sulfurization of thermally evaporated molybdenum oxide (MoO{sub 3}) thin film. Scanning transmission electron microscope studies reveal atomic level structure of the synthesized high quality MoS{sub 2} crystals. In the prospect of a memory device fabrication, poly(methyl methacrylate) (PMMA) is used as an insulating dielectric material as well as a supporting layer to transfer the MoS{sub 2} crystals. In the fabricated device, PMMA-MoS{sub 2} and graphene layers act as the functional and electrode materials, respectively. Distinctive bistable electrical switching and nonvolatile rewritable memory effect is observed in the fabricated PMMA-MoS{sub 2}/graphene heterostructure. The developed material system and demonstrated memory device fabrication can be significant for next generation data storage applications.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2015

Solution-processed Al-chelated gelatin for highly transparent non-volatile memory applications

Using the biomaterial of Al-chelated gelatin (ACG) prepared by sol-gel method in the ITO/ACG/ITO structure, a highly transparent resistive random access memory (RRAM) was obtained. The transmittance of the fabricated device is approximately 83% at 550 nm while that of Al/gelatin/ITO is opaque. As to the ITO/gelatin/ITO RRAM, no resistive switching behavior can be seen. The ITO/ACG/ITO RRAM shows high ON/OFF current ratio (>10{sup 5}), low operation voltage, good uniformity, and retention characteristics at room temperature and 85 °C. The mechanism of the ACG-based memory devices is presented. The enhancement of these electrical properties can be attributed to the chelate effect of Al ions with gelatin. Results show that transparent ACG-based memory devices possess the potential for next-generation resistive memories and bio-electronic applications.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Memory operation devices based on light-illumination ambipolar carbon-nanotube thin-film-transistors

We report the memory operation behavior of a light illumination ambipolar single-walled carbon nanotube thin film field-effect transistors devices. In addition to the high electronic-performance, such an on/off transistor-switching ratio of 10{sup 4} and an on-conductance of 18 μS, these memory devices have shown a high retention time of both hole and electron-trapping modes, reaching 2.8 × 10{sup 4} s at room temperature. The memory characteristics confirm that light illumination and electrical field can act as an independent programming/erasing operation method. This could be a fundamental step toward achieving high performance and stable operating nanoelectronic memory devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Low-power resistive random access memory by confining the formation of conducting filaments

Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiO{sub x}/silver nanoparticles/TiO{sub x}/AlTiO{sub x}, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiO{sub x} layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2016

Effect of electrode material on characteristics of non-volatile resistive memory consisting of Ag{sub 2}S nanoparticles

In this study, Ag{sub 2}S nanoparticles are synthesized and used as the active material for two-terminal resistance switching memory devices. Sintered Ag{sub 2}S films are successfully crystallized on plastic substrates with synthesized Ag{sub 2}S nanoparticles, after a relatively low-temperature sintering process (200 °C). After the sintering process, the crystallite size is increased from 6.8 nm to 80.3 nm. The high ratio of surface atoms to inner atoms of nanoparticles reduces the melting point temperature, deciding the sintering process temperature. In order to investigate the resistance switching characteristics, metal/Ag{sub 2}S/metal structures are fabricated and tested. The effect of the electrode material on the non-volatile resistive memory characteristics is studied. The bottom electrochemically inert materials, such as Au and Pt, were critical for maintaining stable memory characteristics. By using Au and Pt inert bottom electrodes, we are able to significantly improve the memory endurance and retention to more than 10{sup 3} cycles and 10{sup 4} sec, respectively.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2021

Impacts of noise and structure on quantum information encoded in a quantum memory

As larger, higher-quality quantum devices are built and demonstrated in quantum information applications, such as quantum computation and quantum communication, the need for high-quality quantum memories to store quantum states becomes ever more pressing. Future quantum devices likely will use a variety of physical hardware, some being used primarily for processing of quantum information and others for storage. Here we study the correlation of the structure of quantum information with physical noise models of various possible quantum memory implementations. Through numerical simulation of different noise models and approximate analytical formulas applied to a variety of interesting quantum states, we provide comparisons between quantum hardware with different structure, including both qubit- and qudit-based quantum memories. Our findings point to simple, experimentally relevant formulas for the relative lifetimes of quantum information in different quantum memories and have relevance to the design of hybrid quantum devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2022

Field-Deployable Quantum Memory for Quantum Networking

High-performance quantum memories are an essential component for regulating temporal events in quantum networks. As a component in quantum-repeaters, they have the potential to support the distribution of entanglement beyond the physical limitations of fiber loss. This will enable key applications such as quantum key distribution, network-enhanced quantum sensing, and distributed quantum computing. Here, we present a quantum memory engineered to meet real-world deployment and scaling challenges. The memory technology utilizes a warm rubidium vapor as the storage medium, and operates at room temperature, without the need for vacuum- and/or cryogenic- support. Here, we demonstrate performance specifications of high-fidelity retrieval (95%) and low operation error (10 –2 ) at a storage time of 160 µs for single-photon level quantum memory operations. We further show a substantially improved storage time (with classical-level light) of up to 1ms by suppressing atomic diffusions. The device is housed in an enclosure with a standard 2U rackmount form factor, and can robustly operate on a day scale in a noisy environment. This result marks an important step toward implementing quantum networks in the field.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2018

Josephson Thermal Memory

In this work, we propose a superconducting thermal memory device that exploits the thermal hysteresis in a flux-controlled temperature-biased superconducting quantum-interference device (SQUID). This system reveals a flux-controllable temperature bistability, which can be used to define two well-distinguishable thermal logic states. We discuss a suitable writing-reading procedure for these memory states. The time of the memory writing operation is expected to be on the order of approximately 0.2 ns for a Nb-based SQUID in thermal contact with a phonon bath at 4.2 K. We suggest a noninvasive readout scheme for the memory states based on the measurement of the effective resonance frequency of a tank circuit inductively coupled to the SQUID. The proposed device paves the way for a practical implementation of thermal logic and computation. The advantage of this proposal is that it represents also an example of harvesting thermal energy in superconducting circuits.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

Memory and rejuvenation in glassy systems

Here, the memory effect in a single crystal spin glass (Cu 0.92 Mn 0.08 ) has been measured using 1 Hz ac susceptibility measurements over a reduced temperature range of 0.4 - 0.7 T g and a model of the memory effect has been developed. A double-waiting-time protocol is carried out where the spin glass is first allowed to age at a temperature below T g , T w$_{1}$ , followed by a second aging 4 K lower, T w$_{2}$ . The 4 K separation is sufficient to ensure rejuvenation has occurred. The model is based on calculating overlaps between the growth of the correlation lengths at the two temperatures. It accounts for the absolute magnitude of the memory effect as a function of both waiting times and temperatures. The data can be explained by the memory loss being a function of the relative change in the correlated volume at the first waiting temperature due to growth in the correlations at the second waiting temperature.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Custodial Chiral Symmetry in a Su-Schrieffer-Heeger Electrical Circuit with Memory

Custodial symmetries are common in the standard model of particle physics. They arise when quantum corrections to a parameter are proportional to the parameter itself. Here, we show that a custodial symmetry of the chiral type is also present in a classical Su-Schrieffer-Heeger (SSH) electrical circuit with memory. In the absence of memory, the SSH circuit supports a symmetry-protected topological edge state. Memory induces nonlinearities that break chiral symmetry explicitly and spread the state across the circuit. However, the resulting state is still protected against perturbations by the ensuing custodial chiral symmetry. Furthermore, these predictions can be verified experimentally and demonstrate the interplay between symmetry and memory.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2019

Tuning crystallographic compatibility to enhance shape memory in ceramics

The extraordinary ability of shape-memory alloys to recover after large imposed deformation motivates efforts to transpose these properties onto ceramics, which would enable practical shape-memory properties at high temperatures and in harsh environments. The theory of mechanical compatibility was utilized to predict promising ceramic candidates in the system (Y 0.5 Ta 0.5 O 2 ) 1–x –(Zr 0.5 Hf 0.5 O 2 ) x , 0.6 < x < 0.85. When these compatibility conditions are met, a reduction in thermal hysteresis by a factor of 2.5, a tripling of deformability, and a 75% enhancement in strain recovery within the shape-memory effect was found. These findings reveal that predicting and optimizing the chemical composition of ceramics to attain improved crystallographic compatibility is a powerful tool for enabling and enhancing their deformability that could ultimately lead to a highly reversible oxide ceramic shape-memory material.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2017

Unraveling Network-induced Memory Contention: Deeper Insights with Machine Learning

Remote Direct Memory Access (RDMA) is expected to be an integral communication mechanism for future exascale systems enabling asynchronous data transfers, so that applications may fully utilize CPU resources while simultaneously sharing data amongst remote nodes. We examine Network-induced Memory Contention (NiMC) on Infiniband networks. We expose the interactions between RDMA, main-memory and cache, when applications and out-of-band services compete for memory resources. We then explore NiMCs resulting impact on application-level performance. For a range of hardware technologies and HPC workloads, we quantify NiMC and show that NiMCs impact grows with scale resulting in up to 3X performance degradation at scales as small as 8K processes even in applications that previously have been shown to be performance resilient in the presence of noise. In addition, this work examines the problem of predicting NiMC's impact on applications by leveraging machine learning and easily accessible performance counters. This approach provides additional insights about the root cause of NiMC and facilitates dynamic selection of potential solutions. Finally, we evaluated three potential techniques to reduce NiMCs impact, namely hardware offloading, core reservation and network throttling.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Distributed-memory lattice H-matrix factorization

We parallelize the LU factorization of a hierarchical low-rank matrix (H-matrix) on a distributed-memory computer. This is much more difficult than the H-matrix-vector multiplication due to the dataflow of the factorization, and it is much harder than the parallelization of a dense matrix factorization due to the irregular hierarchical block structure of the matrix. Block low-rank (BLR) format gets rid of the hierarchy and simplifies the parallelization, often increasing concurrency. However, this comes at a price of losing the near-linear complexity of the H-matrix factorization. In this work, we propose to factorize the matrix using a “lattice H-matrix” format that generalizes the BLR format by storing each of the blocks (both diagonals and off-diagonals) in the H-matrix format. These blocks stored in the H-matrix format are referred to as lattices. Thus, this lattice format aims to combine the parallel scalability of BLR factorization with the near-linear complexity of H-matrix factorization. We first compare factorization performances using the H-matrix, BLR, and lattice H-matrix formats under various conditions on a shared-memory computer. Our performance results show that the lattice format has storage and computational complexities similar to those of the H-matrix format, and hence a much lower cost of factorization than BLR. In conclusion, we then compare the BLR and lattice H-matrix factorization on distributed-memory computers. Our performance results demonstrate that compared with BLR, the lattice format with the lower cost of factorization may lead to faster factorization on the distributed-memory computer.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2013

Collective Memory Transfers for Multi-Core Chips

Future performance improvements for microprocessors have shifted from clock frequency scaling towards increases in on-chip parallelism. Performance improvements for a wide variety of parallel applications require domain-decomposition of data arrays from a contiguous arrangement in memory to a tiled layout for on-chip L1 data caches and scratchpads. How- ever, DRAM performance suffers under the non-streaming access patterns generated by many independent cores. We propose collective memory scheduling (CMS) that actively takes control of collective memory transfers such that requests arrive in a sequential and predictable fashion to the memory controller. CMS uses the hierarchically tiled arrays formal- ism to compactly express collective operations, which greatly improves programmability over conventional prefetch or list- DMA approaches. CMS reduces application execution time by up to 32% and DRAM read power by 2.2×, compared to a baseline DMA architecture such as STI Cell.

97 MATHEMATICS AND COMPUTING↗