Results for “logic” — Page 30

NASA NTRS1992

Optically intraconnected computer employing dynamically reconfigurable holographic optical element

An optically intraconnected computer and a reconfigurable holographic optical element employed therein. The basic computer comprises a memory for holding a sequence of instructions to be executed; logic for accessing the instructions in sequence; logic for determining for each the instruction the function to be performed and the effective address thereof; a plurality of individual elements on a common support substrate optimized to perform certain logical sequences employed in executing the instructions; and, element selection logic connected to the logic determining the function to be performed for each the instruction for determining the class of each function and for causing the instruction to be executed by those the elements which perform those associated the logical sequences affecting the instruction execution in an optimum manner. In the optically intraconnected version, the element selection logic is adapted for transmitting and switching signals to the elements optically.

Bergman, Larry A.↗

NASA NTRS2018

From Formal Requirements to Highly Assured Software for Unmanned Aircraft Systems

Operational requirements of safety-critical systems are often written in restricted specification logics. These restricted logics are amenable to automated analysis techniques such as model-checking, but are not rich enough to express complex requirements of unmanned systems. This short paper advocates for the use of expressive logics, such as higher-order logic, to specify the complex operational requirements and safety properties of unmanned systems. These rich logics are less amenable to automation and, hence, require the use of interactive theorem proving techniques. However, these logics support the formal verification of complex requirements such as those involving the physical environment. Moreover, these logics enable validation techniques that increase con dence in the correctness of numerically intensive software. These features result in highly-assured software that may be easier to certify. The feasibility of this approach is illustrated with examples drawn for NASA's unmanned aircraft systems.

Munoz, Cesar↗

NASA NTRS1994

Groundspeed filtering for CTAS

Ground speed is one of the radar observables which is obtained along with position and heading from NASA Ames Center radar. Within the Center TRACON Automation System (CTAS), groundspeed is converted into airspeed using the wind speeds which CTAS obtains from the NOAA weather grid. This airspeed is then used in the trajectory synthesis logic which computes the trajectory for each individual aircraft. The time history of the typical radar groundspeed data is generally quite noisy, with high frequency variations on the order of five knots, and occasional 'outliers' which can be significantly different from the probable true speed. To try to smooth out these speeds and make the ETA estimate less erratic, filtering of the ground speed is done within CTAS. In its base form, the CTAS filter is a 'moving average' filter which averages the last ten radar values. In addition, there is separate logic to detect and correct for 'outliers', and acceleration logic which limits the groundspeed change in adjacent time samples. As will be shown, these additional modifications do cause significant changes in the actual groundspeed filter output. The conclusion is that the current ground speed filter logic is unable to track accurately the speed variations observed on many aircraft. The Kalman filter logic however, appears to be an improvement to the current algorithm used to smooth ground speed variations, while being simpler and more efficient to implement. Additional logic which can test for true 'outliers' can easily be added by looking at the difference in the a priori and post priori Kalman estimates, and not updating if the difference in these quantities is too large.

Slater, Gary L.↗

NASA NTRS1995

Circuit for high resolution decoding of multi-anode microchannel array detectors

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Kasle, David B.↗

NASA NTRS2002

An Overview of the Runtime Verification Tool Java PathExplorer

We present an overview of the Java PathExplorer runtime verification tool, in short referred to as JPAX. JPAX can monitor the execution of a Java program and check that it conforms with a set of user provided properties formulated in temporal logic. JPAX can in addition analyze the program for concurrency errors such as deadlocks and data races. The concurrency analysis requires no user provided specification. The tool facilitates automated instrumentation of a program's bytecode, which when executed will emit an event stream, the execution trace, to an observer. The observer dispatches the incoming event stream to a set of observer processes, each performing a specialized analysis, such as the temporal logic verification, the deadlock analysis and the data race analysis. Temporal logic specifications can be formulated by the user in the Maude rewriting logic, where Maude is a high-speed rewriting system for equational logic, but here extended with executable temporal logic. The Maude rewriting engine is then activated as an event driven monitoring process. Alternatively, temporal specifications can be translated into efficient automata, which check the event stream. JPAX can be used during program testing to gain increased information about program executions, and can potentially furthermore be applied during operation to survey safety critical systems.

Havelund, Klaus↗

NASA NTRS2003

EAGLE can do Efficient LTL Monitoring

We briefly present a rule-based framework, called EAGLE, that has been shown to be capable of defining and implementing finite trace monitoring logics, including future and past time temporal logic, extended regular expressions, real-time logics, interval logics, forms of quantified temporal logics, and so on. In this paper we show how EAGLE can do linear temporal logic (LTL) monitoring in an efficient way. We give an upper bound on the space and time complexity of this monitoring.

Barringer, Howard↗

NASA NTRS2003

Rule-Based Runtime Verification

We present a rule-based framework for defining and implementing finite trace monitoring logics, including future and past time temporal logic, extended regular expressions, real-time logics, interval logics, forms of quantified temporal logics, and so on. Our logic, EAGLE, is implemented as a Java library and involves novel techniques for rule definition, manipulation and execution. Monitoring is done on a state-by-state basis, without storing the execution trace.

Barringer, Howard↗

NASA NTRS2004

Program Monitoring with LTL in EAGLE

We briefly present a rule-based framework called EAGLE, shown to be capable of defining and implementing finite trace monitoring logics, including future and past time temporal logic, extended regular expressions, real-time and metric temporal logics (MTL), interval logics, forms of quantified temporal logics, and so on. In this paper we focus on a linear temporal logic (LTL) specialization of EAGLE. For an initial formula of size m, we establish upper bounds of O(m(sup 2)2(sup m)log m) and O(m(sup 4)2(sup 2m)log(sup 2) m) for the space and time complexity, respectively, of single step evaluation over an input trace. This bound is close to the lower bound O(2(sup square root m) for future-time LTL presented. EAGLE has been successfully used, in both LTL and metric LTL forms, to test a real-time controller of an experimental NASA planetary rover.

Barringer, Howard↗

NASA NTRS2000

Resolver to 360.degree. linear analog converter and method

The converter produces a linear analog signal that is linearly proportional to a shaft angle of a resolver over 360.degree.. An excitation cosine signal supplied to the resolver and a response cosine signal received from the output windings of the resolver are converted to logic level signals. Digital logic is performed on the logic level signals in a programmable digital logic device to produce a logic level pulse-width modulated signal. The logic level pulse-width modulated signal is used to control a switch to switch between two reference voltage levels to produce a pulse-width modulated signal, which is filtered and buffered to produce the linear analog signal.

Alhorn, Dean C.↗

NASA NTRS2008

Scheme for Quantum Computing Immune to Decoherence

A constructive scheme has been devised to enable mapping of any quantum computation into a spintronic circuit in which the computation is encoded in a basis that is, in principle, immune to quantum decoherence. The scheme is implemented by an algorithm that utilizes multiple physical spins to encode each logical bit in such a way that collective errors affecting all the physical spins do not disturb the logical bit. The scheme is expected to be of use to experimenters working on spintronic implementations of quantum logic. Spintronic computing devices use quantum-mechanical spins (typically, electron spins) to encode logical bits. Bits thus encoded (denoted qubits) are potentially susceptible to errors caused by noise and decoherence. The traditional model of quantum computation is based partly on the assumption that each qubit is implemented by use of a single two-state quantum system, such as an electron or other spin-1.2 particle. It can be surprisingly difficult to achieve certain gate operations . most notably, those of arbitrary 1-qubit gates . in spintronic hardware according to this model. However, ironically, certain 2-qubit interactions (in particular, spin-spin exchange interactions) can be achieved relatively easily in spintronic hardware. Therefore, it would be fortunate if it were possible to implement any 1-qubit gate by use of a spin-spin exchange interaction. While such a direct representation is not possible, it is possible to achieve an arbitrary 1-qubit gate indirectly by means of a sequence of four spin-spin exchange interactions, which could be implemented by use of four exchange gates. Accordingly, the present scheme provides for mapping any 1-qubit gate in the logical basis into an equivalent sequence of at most four spin-spin exchange interactions in the physical (encoded) basis. The complexity of the mathematical derivation of the scheme from basic quantum principles precludes a description within this article; it must suffice to report that the derivation provides explicit constructions for finding the exchange couplings in the physical basis needed to implement any arbitrary 1-qubit gate. These constructions lead to spintronic encodings of quantum logic that are more efficient than those of a previously published scheme that utilizes a universal but fixed set of gates.

Williams, Colin↗

NASA NTRS2018

Runtime Assurance Protection for Advanced Turbofan Engine Control

This paper describes technical progress made in the application of run time assurance (RTA) methods to turbofan engines with advanced propulsion control algorithms that are employed to improve engine performance. It is assumed that the advanced algorithms cannot be fully certified using current verification and validation approaches and therefore need to be continually monitored by an RTA system that ensures safe operation. However, current turbofan engine control systems utilize engine protection logic for safe combustion dynamics and stable airflow through the engine. It was determined that the engine protection logic should continue to be used to provide system safety and should be considered as a part of the overall RTA system. The additional function that an RTA system provides is to perform diagnostics on anomalous conditions to determine if these conditions are being caused by errors in the advanced controller. If this is the case, the RTA system switches operation to a trusted reversionary controller. Initial studies were performed to demonstrate this benefit. The other focus was to improve the performance of the engine protection logic, which was deemed too conservative and reduced engine performance during transient operations. It was determined that the conservative response was due to poor tuning of one of the controller channels within the protection logic. An automatic tuning algorithm was implemented to optimize the protection logic control gains based on minimizing tracking error. Improved tracking responses were observed with no change to the existing protection logic control architecture.

runtime monitoring↗

NASA NTRSDate not supplied

Transient Optimization of a Gas Turbine Engine

Gas turbine engines are the primary power plants for modern commercial aircraft. Transients prompted by significant changes in thrust or power demand are common and unavoidable. Extreme transient scenarios such as those associated with a go-around during a landing attempt are possible and must be accounted for in the design of the engine and its controller. Engine transients tend to cause a reduction in compressor operability margin, which must be addressed by the engine control system and accounted for in the engine design to prevent events such as compressor stall/surge and combustor blow out. Transient operability concerns typically lead to compromises in the engine design that sacrifice efficiency and/or limit responsiveness. Transient operability is typically managed by logic that limits the fuel flow command. If this logic is not optimized, then the potential for valuable performance could be lost. This study presents a strategy for optimizing the transient limit logic and proposes a strategy for updating the control logic over the lifespan of the engine. The results demonstrate significant improvements in transient operability. For example, of the results at sea level static conditions demonstrated a 31% reduction in the usage of the high pressure compressor operability stack during a snap acceleration transient. Furthermore, a reinforcement learning algorithm is demonstrated to modify the transient logic as the engine degrades to minimize response time while respecting a prescribed compressor operability margin limit. A simple demonstration of the reinforcement learning algorithm resulted in a thrust response time reduction of ~11.8%.

transient↗

NASA NTRSDate not supplied

Transient Optimization of a Gas Turbine Engine

Gas turbine engines are the primary power plants for modern commercial aircraft. Transients prompted by significant changes in thrust or power demand are common and unavoidable. Extreme transient scenarios such as those associated with a go-around during a landing attempt are possible and must be accounted for in the design of the engine and its controller. Engine transients tend to cause a reduction in compressor operability margin, which must be addressed by the engine control system and accounted for in the engine design to prevent events such as compressor stall/surge and combustor blow out. Transient operability concerns typically lead to compromises in the engine design that sacrifice efficiency and/or limit responsiveness. Transient operability is typically managed by logic that limits the fuel flow command. If this logic is not optimized, then the potential for valuable performance could be lost. This study presents a strategy for optimizing the transient limit logic and proposes a strategy for updating the control logic over the lifespan of the engine. The results demonstrate significant improvements in transient operability. For example, of the results at sea level static conditions demonstrated a 31% reduction in the usage of the high pressure compressor operability stack during a snap acceleration transient. Furthermore, a reinforcement learning algorithm is demonstrated to modify the transient logic as the engine degrades to minimize response time while respecting a prescribed compressor operability margin limit. A simple demonstration of the reinforcement learning algorithm resulted in a thrust response time reduction of ~11.8%.

transient↗

NASA NTRSDate not supplied

Transient Optimization of a Gas Turbine Engine

Gas turbine engines are the primary power plants for modern commercial aircraft. Transients prompted by significant changes in thrust or power demand are common and unavoidable. Extreme transient scenarios such as those associated with a go-around during a landing attempt are possible and must be accounted for in the design of the engine and its controller. Engine transients tend to cause a reduction in compressor operability margin, which must be addressed by the engine control system and accounted for in the engine design to prevent events such as compressor stall/surge and combustor blow out. Transient operability concerns typically lead to compromises in the engine design that sacrifice efficiency and/or limit responsiveness. Transient operability is typically managed by logic that limits the fuel flow command. If this logic is not optimized, then the potential for valuable performance could be lost. This study presents a strategy for optimizing the transient limit logic and proposes a strategy for updating the control logic over the lifespan of the engine. The results demonstrate significant improvements in transient operability. For example, of the results at sea level static conditions demonstrated a 31% reduction in the usage of the high pressure compressor operability stack during a snap acceleration transient. Furthermore, a reinforcement learning algorithm is demonstrated to modify the transient logic as the engine degrades to minimize response time while respecting a prescribed compressor operability margin limit. A simple demonstration of the reinforcement learning algorithm resulted in a thrust response time reduction of ~11.8%.

transient↗

NASA NTRS1987

Failure detection and identification for a reconfigurable flight control system

Failure detection and identification logic for a fault-tolerant longitudinal control system were investigated. Aircraft dynamics were based upon the cruise condition for a hypothetical transonic business jet transport configuration. The fault-tolerant control system consists of conventional control and estimation plus a new outer loop containing failure detection, identification, and reconfiguration (FDIR) logic. It is assumed that the additional logic has access to all measurements, as well as to the outputs of the control and estimation logic. The pilot may also command the FDIR logic to perform special tests.

Dallery, Francois↗

NASA NTRS1989

Test aspects of the JPL Viterbi decoder

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Breuer, M. A.↗

NASA NTRS1990

Genetic algorithm based fuzzy control of spacecraft autonomous rendezvous

The U.S. Bureau of Mines is currently investigating ways to combine the control capabilities of fuzzy logic with the learning capabilities of genetic algorithms. Fuzzy logic allows for the uncertainty inherent in most control problems to be incorporated into conventional expert systems. Although fuzzy logic based expert systems have been used successfully for controlling a number of physical systems, the selection of acceptable fuzzy membership functions has generally been a subjective decision. High performance fuzzy membership functions for a fuzzy logic controller that manipulates a mathematical model simulating the autonomous rendezvous of spacecraft are learned using a genetic algorithm, a search technique based on the mechanics of natural genetics. The membership functions learned by the genetic algorithm provide for a more efficient fuzzy logic controller than membership functions selected by the authors for the rendezvous problem. Thus, genetic algorithms are potentially an effective and structured approach for learning fuzzy membership functions.

Karr, C. L.↗

NASA NTRS2002

What is a Question?

A given question can be defined in terms of the set of statements or assertions that answer it. Application of the logic of inference to this set of assertions allows one to derive the logic of inquiry among questions. There are interesting symmetries between the logics of inference and inquiry; where probability describes the degree to which a premise implies an assertion, there exists an analogous quantity that describes the bearing or relevance that a question has on an outstanding issue. These have been extended to suggest that the logic of inquiry results in functional relationships analogous to, although more general than, those found in information theory. Employing lattice theory, I examine in greater detail the structure of the space of assertions and questions demonstrating that the symmetries between the logical relations in each of the spaces derive directly from the lattice structure. Furthermore, I show that while symmetries between the spaces exist, the two lattices are not isomorphic. The lattice of assertions is described by a Boolean lattice 2(sup N) whereas the lattice of real questions is shown to be a sublattice of the free distributive lattice FD(N) = 2(sup 2(sup N)). Thus there does not exist a one-to-one mapping of assertions to questions, there is no reflection symmetry between the two spaces, and questions in general do not possess unique complements. Last, with these lattice structures in mind, I discuss the relationship between probability, relevance and entropy.

Knuth, Kevin H.↗