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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

The level-1 trigger for the SuperCDMS experiment at SNOLAB

The SuperCDMS SNOLAB dark matter search experiment aims to be sensitive to energy depositions down to Script O(1 eV). This imposes requirements on the resolution, signal efficiency, and noise rejection of the trigger system. To accomplish this, the SuperCDMS level-1 trigger system is implemented in an FPGA on a custom PCB. A time-domain optimal filter algorithm realized as a finite impulse response filter provides a baseline resolution of 0.38 times the standard deviation of the noise, σn, and a 99.9% trigger efficiency for signal amplitudes of 1.1 σ n in typical noise conditions. Embedded in a modular architecture, flexible trigger logic enables reliable triggering and vetoing in a dead-time-free manner for a variety of purposes and run conditions. The trigger architecture and performance are detailed in this article.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1990

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗
NASA NTRS2003

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

Kaplan, Steven B.↗
NASA NTRS2011

High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors

Exponential growth in microelectronics technology such as field-programmable gate arrays (FPGAs) has enabled high-performance spaceborne instruments with increasing onboard data processing capabilities. As a commonly used digital signal processing (DSP) building block, fast Fourier transform (FFT) has been of great interest in onboard data processing applications, which needs to strike a reasonable balance between high-performance (throughput, block size, etc.) and low resource usage (power, silicon footprint, etc.). It is also desirable to be designed so that a single design can be reused and adapted into instruments with different requirements. The Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture was developed, in which the high-throughput benefits of the parallel FFT structure and the low resource usage of Singleton s single butterfly method is exploited. The result is a wide-kernel, multipass, adaptive FFT architecture. The 32K-point MPWK-FFT architecture includes 32 radix-2 butterflies, 64 FIFOs to store the real inputs, 64 FIFOs to store the imaginary inputs, complex twiddle factor storage, and FIFO logic to route the outputs to the correct FIFO. The inputs are stored in sequential fashion into the FIFOs, and the outputs of each butterfly are sequentially written first into the even FIFO, then the odd FIFO. Because of the order of the outputs written into the FIFOs, the depth of the even FIFOs, which are 768 each, are 1.5 times larger than the odd FIFOs, which are 512 each. The total memory needed for data storage, assuming that each sample is 36 bits, is 2.95 Mbits. The twiddle factors are stored in internal ROM inside the FPGA for fast access time. The total memory size to store the twiddle factors is 589.9Kbits. This FFT structure combines the benefits of high throughput from the parallel FFT kernels and low resource usage from the multi-pass FFT kernels with desired adaptability. Space instrument missions that need onboard FFT capabilities such as the proposed DESDynl, SWOT (Surface Water Ocean Topography), and Europa sounding radar missions would greatly benefit from this technology with significant reductions in non-recurring cost and risk.

NguyenKobayashi, Kayla↗
DOE OSTI2023

Human-Building Collaboration: Toward lighting enabled collaborative system design

The profession of lighting design is evolving as contemporary lighting systems increasingly rely on cutting-edge computational technologies, sensors, and IOT systems. This trend requires designers to incorporate ideas of automation, dynamic controls, and user-system interaction into their design logic. However, real-time lighting simulations are constrained by inherent limitations arising from the reductive assumptions inevitably introduced in simulated lighting environments. This raises the question of how can designers account for the discrepancies between simulated and real lighting environments, and how can collaboration between humans and autonomous lighting systems bridge this gap. To address this question, we propose a protocol for designing collaborative interactions between humans and systems. Furthermore, this protocol builds on the Human-Lighting System Interaction Framework and demonstrates how human and system intelligence can be combined to fine-tune lighting qualities in a given space. Our paper shows how interactive lighting systems can customize lighting based on user preferences in real-time and how global lighting configurations can be adjusted over time. Specifically, we demonstrate: a) Human-system collaboration assumptions and goals, as well as how the protocol can be integrated into digitally programmable lighting systems. b) Implementations of collaboration that reveal how system autonomy, performance, and user experience are improved over short and long-term timeframes. c) How lighting design can be enhanced beyond simulation-driven design optimization capacities. The associated affordances and limitations are discussed with respect to existing lighting simulation design frameworks.

autonomous systems↗
DOE OSTI2024

Synthesis of Correct Digital Controller Models from Specifications by Model Transformation (21-0320)

The design of high consequence controllers (in weapons systems, autonomy, etc.) that do what they are supposed to do is a significant challenge. Testing simply does not come close to meeting the requirements for assurance. Today circuit designers at Sandia (and elsewhere) typically capture the core behavior of their components using state models in tools such as STATEFLOW. They then check that their models meet certain requirements (e.g. “The system bus must not deadlock” or “both traffic lights at an intersection must not be green at the same time”) using tools called model checkers. If the model checker returns “yes” then the property is guaranteed to be satisfied by the model. However, there are several drawbacks to this industry practice: (1) there is a lot of detail to get right, this is particularly challenging when there are multiple components requiring complex coordination (2) any errors returned by the model checker have to be traced back through the design and fixed, necessitating rework, (3) there are severe scalability problems with this approach, particularly when dealing with concurrency. All this places high demands on the designers who now face not only an accelerated schedule but also controllers of increasing complexity. This report describes a new and fundamentally different approach to the construction of safety-critical digital controllers. Instead of directly constructing a complete model and then trying to verify it, the designer can start with an initial abstract (think “sketch”) model plus the requirements, from which a correct concrete model is automatically synthesized. There is no need for post-hoc verification of required functional properties. Having tool to carry this out will significantly impact the nation’s ability to ensure the safety of high-consequence digital systems. The approach has been implemented in a prototype tool, along with a suite of examples, including ones that reflect actual problems faced by designers. Our approach operates on a variant of Statecharts developed at Sandia called Qspecs. Statecharts are a widely used formalism for developing concurrent reactive systems, supporting scalability through allowing state models containing composite states, which are the serial or parallel composition of substates which can themselves contain statecharts. Statecharts enable an incremental style of development, in which states are progressively refined to incorporate greater detail in an incremental model of software development. Our approach formulates a set of constraints from the structure of the models and the requirements and propagates these constraints to a fixpoint. The solution to the constraints is an inductive invariant along with guards on the transitions. We also show how our approach extends to implementation refinement, decomposition, composition, and elaboration. We currently handle safety requirements written in LTL (Linear Temporal Logic)

42 ENGINEERING↗
DOE OSTI2025

Harnessing ferro-valleytricity in pentalayer rhombohedral graphene for memory and compute

Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving pentalayer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable ferro-valleytricity of pentalayer rhombohedral graphene to develop nonvolatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less nonvolatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, nondestructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ∼6 nW required per write operation and ∼2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed nonvolatile memory array without modifying the peripheral circuitry. In conclusion, our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.

2D materials↗
NASA NTRS2011

High-Performance Wireless Telemetry

Prior technology for machinery data acquisition used slip rings, FM radio communication, or non-real-time digital communication. Slip rings are often noisy, require much space that may not be available, and require access to the shaft, which may not be possible. FM radio is not accurate or stable, and is limited in the number of channels, often with channel crosstalk, and intermittent as the shaft rotates. Non-real-time digital communication is very popular, but complex, with long development time, and objections from users who need continuous waveforms from many channels. This innovation extends the amount of information conveyed from a rotating machine to a data acquisition system while keeping the development time short and keeping the rotating electronics simple, compact, stable, and rugged. The data are all real time. The product of the number of channels, times the bit resolution, times the update rate, gives a data rate higher than available by older methods. The telemetry system consists of a data-receiving rack that supplies magnetically coupled power to a rotating instrument amplifier ring in the machine being monitored. The ring digitizes the data and magnetically couples the data back to the rack, where it is made available. The transformer is generally a ring positioned around the axis of rotation with one side of the transformer free to rotate and the other side held stationary. The windings are laid in the ring; this gives the data immunity to any rotation that may occur. A medium-frequency sine-wave power source in a rack supplies power through a cable to a rotating ring transformer that passes the power on to a rotating set of electronics. The electronics power a set of up to 40 sensors and provides instrument amplifiers for the sensors. The outputs from the amplifiers are filtered and multiplexed into a serial ADC. The output from the ADC is connected to another rotating ring transformer that conveys the serial data from the rotating section to the stationary section. From there, a cable conveys the serial data to the remote rack, where it is reconditioned to logic level specifications, de-serialized, and converted back to analog. In the rotating electronics are code generators to indicate the beginning of files for data synchronization.

Griebeler, Elmer↗
DOE OSTI2020

Scalable Substitutional Re‐Doping and its Impact on the Optical and Electronic Properties of Tungsten Diselenide

Abstract Reliable, controlled doping of 2D transition metal dichalcogenides will enable the realization of next‐generation electronic, logic‐memory, and magnetic devices based on these materials. However, to date, accurate control over dopant concentration and scalability of the process remains a challenge. Here, a systematic study of scalable in situ doping of fully coalesced 2D WSe 2 films with Re atoms via metal–organic chemical vapor deposition is reported. Dopant concentrations are uniformly distributed over the substrate surface, with precisely controlled concentrations down to <0.001% Re achieved by tuning the precursor partial pressure. Moreover, the impact of doping on morphological, chemical, optical, and electronic properties of WSe 2 is elucidated with detailed experimental and theoretical examinations, confirming that the substitutional doping of Re at the W site leads to n‐type behavior of WSe 2 . Transport characteristics of fabricated back‐gated field‐effect‐transistors are directly correlated to the dopant concentration, with degrading device performances for doping concentrations exceeding 1% of Re. The study demonstrates a viable approach to introducing true dopant‐level impurities with high precision, which can be scaled up to batch production for applications beyond digital electronics.

Kozhakhmetov, Azimkhan↗
DOE OSTI2025

Ring Pull Strain Analysis Version 1.1

This report details an analysis package, Ring Pull Strain Analysis (RPSA), that can be used to present and quantify digital image correlation (DIC) data as it relates to a gaugeless ring pull test. Gaugeless ring pull is a testing technique for mechanical testing of small annular samples, usually cut from a thin-walled tube. DIC data is often necessary for this kind of test because bending moments present on the ring cause a non-uniform strain distribution and localized measurements are necessary. In addition, the annular geometry of a ring lends itself to a polar representation, which is not present with typical DIC analysis methods. RPSA was made to calculate and plot the polar representation of strain from standard pre-processed DIC data of a gaugeless ring pull test. Further analysis can be done on ring pull including a quasi-uniaxial tensile analysis and coating analysis, which are also performed by RPSA. In addition, due to the universality of DIC plotting and ring pull test analysis, RPSA can accommodate a wide variety of tests, though it is tailored for ring pull testing. This report details how RPSA works, including the theory, assumptions, and logic behind the calculations and the structure of the program.

36 MATERIALS SCIENCE↗
DOE OSTI2025

A comprehensive academic and industrial survey of blockchain technology for the energy sector using fuzzy Einstein decision-making

The global energy sector is undergoing a significant transformation driven by decarbonization and digitalization, leading to the emergence of Distributed Ledger Technology (DLT) — particularly blockchain — as a promising tool for enhancing transparency, security, and efficiency in modern power systems. This study aims to provide a comprehensive academic and industrial survey of blockchain applications in the energy sector and develop a robust decision-making framework to identify and prioritize the most promising real-world use cases based on multidisciplinary criteria. A three-stage methodology was adopted: (i) a literature and market review encompassing over 300 academic publications and commercial blockchain initiatives in energy, (ii) an in-depth evaluation of the evolution and viability of blockchain initiatives in energy with the help of expert surveys, and (iii) a novel decision-making model using a q-rung orthopair fuzzy Multi-Attributive Border Approximation (q-ROF-MABAC) method under the Einstein operator. The results were compared with existing decision models to validate consistency and robustness. Nine key blockchain use case categories were identified and ranked based on technical, economic, and governance dimensions. The results demonstrated that integrating expert insights into a fuzzy logic framework helps filter out overhyped claims in the literature and prioritize realistic and high-impact applications such as green certificates, grid services, and peer-to-peer energy trading. The model’s rankings remained stable across varying weight configurations, confirming the robustness of the methodology. This study provides an evidence-based decision-support tool for researchers, industry stakeholders, and policymakers to better understand, evaluate, and adopt blockchain technologies in the energy sector.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2022

How Can Construction Process Simulation Modeling Aid the Integration of Lean Principles in the Factory-Built Housing Industry?

New and existing factories that produce and deliver factory-built housing can benefit from construction process simulation modeling to explore the integration of Lean principles in their operations. Construction process simulation modeling provides digital or virtual recreations of the real-world factory environments to visualize, quantify, analyze, and optimize their underlying behavior, including factory productivity, material flow, labor dynamics, bottlenecks, and work scope. One of the key benefits of process simulation modeling is the ability to create and compare "what-if" scenarios, including integrating Lean principles such as reducing waste (for example, transportation, waiting), line balancing, and just-in-time concepts. In general, three process simulation methods are widely used: discrete event simulation (DES), agentbased modeling (ABM), and system dynamics (SD). Myriad process simulation software also is available, but depending on the industry, complexity of the system, and purposes of the simulation, some software might be more appropriate. Similar to how computer-aided design (CAD) software such as AutoCAD and Rhinoceros enable building design of modular or factory-built housing, process simulation modeling software such as jStrobe, ProModel, and AnyLogic can enable factory design of new and existing factories to deliver modular affordable housing at scale, as opposed to traditional site-built construction. Software with DES capabilities can help generate a process model that is a logical representation of resources and activities in a factory. Software with CAD-DES integration can leverage product-process data integration to help spatially visualize a DES model of the factory in the CAD environment. Software with multimethod simulation capabilities, widely used in the manufacturing industry, brings together DES, ABM, and SD in a single platform that allows visualization, quantification, analyses, and optimization at varying data fidelities. Near-real-time data from an existing factory can be directly plugged into multimethod simulation software so that the construction process simulation model is a near-accurate representation of the real-world factory conditions. This report provides insights into the use of simulation as an aid to integrate Lean concepts in factories, including guidelines for selecting the appropriate process simulation modeling method and software. These insights have been developed as part of ongoing process simulation modeling research, development, and demonstration projects at the U.S. Department of Housing and Urban Development, the U.S. Department of Energy, and the National Renewable Energy Laboratory focused on how process simulation models can enable better integration of resilience, energy efficiency, and low-carbon design strategies.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
NASA NTRS1989

Long period pseudo random number sequence generator

A circuit for generating a sequence of pseudo random numbers, (A sub K). There is an exponentiator in GF(2 sup m) for the normal basis representation of elements in a finite field GF(2 sup m) each represented by m binary digits and having two inputs and an output from which the sequence (A sub K). Of pseudo random numbers is taken. One of the two inputs is connected to receive the outputs (E sub K) of maximal length shift register of n stages. There is a switch having a pair of inputs and an output. The switch outputs is connected to the other of the two inputs of the exponentiator. One of the switch inputs is connected for initially receiving a primitive element (A sub O) in GF(2 sup m). Finally, there is a delay circuit having an input and an output. The delay circuit output is connected to the other of the switch inputs and the delay circuit input is connected to the output of the exponentiator. Whereby after the exponentiator initially receives the primitive element (A sub O) in GF(2 sup m) through the switch, the switch can be switched to cause the exponentiator to receive as its input a delayed output A(K-1) from the exponentiator thereby generating (A sub K) continuously at the output of the exponentiator. The exponentiator in GF(2 sup m) is novel and comprises a cyclic-shift circuit; a Massey-Omura multiplier; and, a control logic circuit all operably connected together to perform the function U(sub i) = 92(sup i) (for n(sub i) = 1 or 1 (for n(subi) = 0).

Wang, Charles C.↗
NASA NTRS2011

Measuring Input Thresholds on an Existing Board

A critical PECL (positive emitter-coupled logic) interface to Xilinx interface needed to be changed on an existing flight board. The new Xilinx input interface used a CMOS (complementary metal-oxide semiconductor) type of input, and the driver could meet its thresholds typically, but not in worst-case, according to the data sheet. The previous interface had been based on comparison with an external reference, but the CMOS input is based on comparison with an internal divider from the power supply. A way to measure what the exact input threshold was for this device for 64 inputs on a flight board was needed. The measurement technique allowed an accurate measurement of the voltage required to switch a Xilinx input from high to low for each of the 64 lines, while only probing two of them. Directly driving an external voltage was considered too risky, and tests done on any other unit could not be used to qualify the flight board. The two lines directly probed gave an absolute voltage threshold calibration, while data collected on the remaining 62 lines without probing gave relative measurements that could be used to identify any outliers. The PECL interface was forced to a long-period square wave by driving a saturated square wave into the ADC (analog to digital converter). The active pull-down circuit was turned off, causing each line to rise rapidly and fall slowly according to the input s weak pull-down circuitry. The fall time shows up as a change in the pulse width of the signal ready by the Xilinx. This change in pulse width is a function of capacitance, pulldown current, and input threshold. Capacitance was known from the different trace lengths, plus a gate input capacitance, which is the same for all inputs. The pull-down current is the same for all inputs including the two that are probed directly. The data was combined, and the Excel solver tool was used to find input thresholds for the 62 lines. This was repeated over different supply voltages and temperatures to show that the interface had voltage margin under all worst case conditions. Gate input thresholds are normally measured at the manufacturer when the device is on a chip tester. A key function of this machine was duplicated on an existing flight board with no modifications to the nets to be tested, with the exception of changes in the FPGA program.

Kuperman, Igor↗
DOE OSTI2023

Superconducting Hyperdimensional Associative Memory Circuit for Scalable Machine Learning

Here we propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of ~ 2-20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78-84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2006

System Would Detect Foreign-Object Damage in Turbofan Engine

A proposed data-fusion system, to be implemented mostly in software, would further process the digitized and preprocessed outputs of sensors in a turbofan engine to detect foreign-object damage (FOD) [more precisely, damage caused by impingement of such foreign objects as birds, pieces of ice, and runway debris]. The proposed system could help a flight crew to decide what, if any, response is necessary to complete a flight safely, and could aid mechanics in deciding what post-flight maintenance action might be needed. The sensory information to be utilized by the proposed system would consist of (1) the output of an accelerometer in an engine-vibration-monitoring subsystem and (2) features extracted from a gas path analysis. ["Gas path analysis" (GPA) is a term of art that denotes comprehensive analysis of engine performance derived from readings of fuel-flow meters, shaft-speed sensors, temperature sensors, and the like.] The acceleration signal would first be processed by a wavelet-transform-based algorithm, using a wavelet created for the specific purpose of finding abrupt FOD-induced changes in noisy accelerometer signals. Two additional features extracted would be the amplitude of vibration (determined via a single- frequency Fourier transform calculated at the rotational speed of the engine), and the rate of change in amplitude due to an FOD-induced rotor imbalance. This system would utilize two GPA features: the fan efficiency and the rate of change of fan efficiency with time. The selected GPA and vibrational features would be assessed by two fuzzy-logic inference engines, denoted the "Gas Path Expert" and the "Vibration Expert," respectively (see Figure 1). Each of these inference engines would generate a "possibility" distribution for occurrence of an FOD event: Each inference engine would assign, to its input information, degrees of membership, which would subsequently be transformed into basic probability assignments for the gas path and vibration components. The outputs of the inference engines would be fused by use of Dempster s combination algorithm (more precisely, an algorithm, based on the Dempster-Shafer-Yager theory of evidence, for fusing uncertain or imprecise information) to provide a reduced body of information to a human or computer decision maker. Figure 2 depicts some outputs generated in response to simulated accelerometer and GPA signals

Torso, James A.↗
DOE OSTI2021

Enabling Pulse-level Programming, Compilation, and Execution in XACC

Noisy gate-model quantum processing units (QPUs) are currently available from vendors over the cloud, and digital quantum programming approaches exist to run low-depth circuits on physical hardware. These digital representations are ultimately lowered to pulse-level instructions by vendor quantum control systems to affect unitary evolution representative of the submitted digital circuit. Vendors are beginning to open this pulse-level control system to the public via specified interfaces. Robust programming methodologies, software frameworks, and backend simulation technologies for this analog model of quantum computation will prove critical to advancing pulse-level control research and development. Prototypical use cases for this include error mitigation, optimal pulse control, and physics-inspired pulse construction. Here we present an extension to the XACC quantum-classical software framework that enables pulse-level programming for superconducting, gate-model quantum computers, and a novel, general, and extensible pulse-level simulation backend for XACC that scales on classical compute clusters via MPI. Our work enables custom backend Hamiltonian definitions and gate-level compilation to available pulses with a focus on performance and scalability. We end with a demonstration of this capability, and show how to use XACC for pertinent pulse-level programming tasks.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2010

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature range and thermal cycling to determine suitability for use in space exploration missions and terrestrial fields under extreme temperature conditions.

Patterson, Richard L.↗