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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Long-haul high rate quantum key distribution

Multiple bit values can be encoded on a single photon in a quantum key distribution (QKD) system using a plurality of sidebands of an optical carrier frequency. Computational and conjugate bases can be defined, and photons decoded based on a selected state from either basis. If n sidebands are available, as many as log2 n bits can be encoded on a single photon. Errors in detected bit values due to selection of an incorrect basis state or other errors can be at least partially corrected by bit distillation to identity bit strings for which a transmitter and a receiver record the same values, without insecure transmission of these values.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS1973

Multimegabit Operation Multiplexer System

The Multimegabit Operation Multiplexer System (MOMS) is a high-data-rate PCM telemetry unit capable of sampling and encoding 60 scanning radiometer and four vidicon channels at 250 kilosamples/second and 5 megasamples/second, respectively. This sampling capacity plus the seven-bit quantization requires a total throughput rate of 40 megasamples/second and 280 megabits/second. To produce these rates efficiently, the system was divided into a pair of identical 140-megabit blocks. A low-power 20-MHz analog multiplexer and analog-to-digital converter were developed together with a video sample-and-hold that features an aperture time error of less than 50 psec. Breadboard testing of these basic building blocks confirmed the design prediction that the total system would consume 27 watts of power. Two 140-megabit output parts are suitable for quadriphase modulation.

Giri, R. R.↗
NASA NTRS1977

Triaxial digital fluxgate magnetometer for NASA applications explorer mission: Results of tests of critical elements

Tests performed to prove the critical elements of the triaxial digital fluxgate magnetometer design were described. A method for improving the linearity of the analog to digital converter portion of the instrument was studied in detail. A sawtooth waveform was added to the signal being measured before the A/D conversion, and averaging the digital readings over one cycle of the sawtooth. It was intended to reduce bit error nonlinearities present in the A/D converter which could be expected to be as much as 16 gamma if not reduced. No such nonlinearities were detected in the output of the instrument which included the feature designed to reduce these nonlinearities. However, a small scale nonlinearity of plus or minus 2 gamma with a 64 gamma repetition rate was observed in the unit tested. A design improvement intended to eliminate this small scale nonlinearity was examined.

Mcleod, M. G.↗
DOE OSTI2024

Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study

GPU memory corruption and in particular double-bit errors (DBEs) remain one of the least understood aspects of HPC system reliability. Albeit rare, their occurrences always lead to job termination and can potentially cost thousands of node-hours, either from wasted computations or as the overhead from regular checkpointing needed to minimize the losses. As supercomputers and their components simultaneously grow in scale, density, failure rates, and environmental footprint, the efficiency of HPC operations becomes both an imperative and a challenge. We examine DBEs using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). Using exploratory data analysis and statistical learning, we extract several insights about memory reliability in such GPUs. We find that GPUs with prior DBE occurrences are prone to experience them again due to otherwise harmless factors, correlate this phenomenon with GPU placement, and suggest manufacturing variability as a factor. On the general population of GPUs, we link DBEs to short- and long-term high power consumption modes while finding no significant correlation with higher temperatures. We also show that the workload type can be a factor in memory’s propensity to corruption.

Oles, Vlad↗
NASA NTRS1974

Augmented burst-error correction for UNICON laser memory

A single-burst-error correction system is described for data stored in the UNICON laser memory. In the proposed system, a long fire code with code length n greater than 16,768 bits was used as an outer code to augment an existing inner shorter fire code for burst error corrections. The inner fire code is a (80,64) code shortened from the (630,614) code, and it is used to correct a single-burst-error on a per-word basis with burst length b less than or equal to 6. The outer code, with b less than or equal to 12, would be used to correct a single-burst-error on a per-page basis, where a page consists of 512 32-bit words. In the proposed system, the encoding and error detection processes are implemented by hardware. A minicomputer, currently used as a UNICON memory management processor, is used on a time-demanding basis for error correction. Based upon existing error statistics, this combination of an inner code and an outer code would enable the UNICON system to obtain a very low error rate in spite of flaws affecting the recorded data.

Lim, R. S.↗
NASA NTRS1974

Digital receiver simulation

Digital simulation of the data link for the Saturn-Uranus spacecraft design is summarized. The data link is a 40 watt, 400 MegaHertz, 44 bit-a-second link, a power starved link, and uses convolution coding. Aspects of the link of particular interest are atmospheric scintillation and the Doppler to data rate ratio. The major characteristics of the scintillation are modeled in terms of tapped delay lines. A candidate system design and receiver design is developed. A computer flow diagram depicting a routine for the error rate and one for acquisition is presented. Various coding algorithms are analyzed since the convolution code is sensitive to the distribution of error and the actual pattern of the error.

Hinrichs, C.↗
NASA NTRS1981

A modified adaptive delta modulator

This paper presents the results of a study in data compression of adaptive delta modulated video signals. The Song mode ADM is first investigated at a sampling rate of 16 Mbits/s and shown not to produce enough redundancy to warrant entropy encoding. A modified adaptive delta modulator algorithm is presented that operates at a sampling rate of 16 Mbits/s and does produce sufficient redundancy to yield a 40-50 percent data compression by using a simple code on 4 bit data blocks. Other techniques such as field interpolation and direct substitution are shown to increase the possible data compression further without noticeable degradation in the two input images used in this investigation. The effects of channel errors in the transmission of packet video over a computer network are considered. A leaky integrator is used to reduce the effects of channel errors in the data bits. It is shown that the effects of channel errors can be reduced by field interpolating those packets that can be shown to contain errors.

Barba, J.↗
NASA NTRS2008

Integrated Performance of Next Generation High Data Rate Receiver and AR4JA LDPC Codec for Space Communications

Low-density parity-check (LDPC) codes are the state-of-the-art in forward error correction (FEC) technology that exhibits capacity approaching performance. The Jet Propulsion Laboratory (JPL) has designed a family of LDPC codes that are similar in structure and therefore, leads to a single decoder implementation. The Accumulate-Repeat-by-4-Jagged- Accumulate (AR4JA) code design offers a family of codes with rates 1/2, 2/3, 4/5 and lengths 1024, 4096, 16384 information bits. Performance is less than one dB from capacity for all combinations.Integrating a stand-alone LDPC decoder with a commercial-off-the-shelf (COTS) receiver faces additional challenges than building a single receiver-decoder unit from scratch. In this work, we outline the issues and show that these additional challenges can be over-come by simple solutions. To demonstrate that an LDPC decoder can be made to work seamlessly with a COTS receiver, we interface an AR4JA LDPC decoder developed on a field-programmable gate array (FPGA) with a modern high data rate receiver and mea- sure the combined receiver-decoder performance. Through optimizations that include an improved frame synchronizer and different soft-symbol scaling algorithms, we show that a combined implementation loss of less than one dB is possible and therefore, most of the coding gain evidence in theory can also be obtained in practice. Our techniques can benefit any modem that utilizes an advanced FEC code.

Cheng, Michael K.↗
NASA NTRS1972

Effects of multipath fading on low data-rate space communications.

Studies have shown that there is a severe signal fading at the turbulent atmosphere of a distant planet such as Venus. The data may be lost during deep fade. It is the objective of this paper to examine the effects of multipath fading on the performance of the noncoherent coded system which is used for the low data-rate space communications especially with the small probes. An exact error probability of the wideband noncoherent MFSK receiver is derived from using the 'Rician' channel model. While the error performance of the receiver is worse than that of the ideal MFSK receiver, as expected, it is interesting to note that the performance degradation due to the multipath fading diminishes as the product of bit duration and IF filter bandwidth becomes large.

Chen, C. H.↗
DOE OSTI2022

Active readout-error mitigation

Mitigating errors is a significant challenge for near-term quantum computers. One of the most important sources of errors is related to the readout of the quantum state into a classical bit stream. A variety of techniques have been proposed to mitigate these errors with post-hoc corrections. Here, we propose a complementary scheme to actively reduce readout errors on a shot-by-shot basis by encoding single qubits, immediately prior to readout, into multiqubit states. The computational resources of our technique are independent of the circuit depth and are compatible with the error rates and connectivity of many current devices. We analyze the potential of our approach using two types of error-correcting codes, and, as a proof of principle, we demonstrate an 80% improvement in readout error on the IBMQ Mumbai quantum computer.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Correlated charge noise and relaxation errors in superconducting qubits

In This report, the central challenge in building a quantum computer is error correction. Unlike classical bits, which are susceptible to only one type of error, quantum bits (“qubits”) are susceptible to two types of error, corresponding to flips of the qubit state about the X- and Z-directions. While the Heisenberg Uncertainty Principle precludes simultaneous monitoring of X- and Z-flips on a single qubit, it is possible to encode quantum information in large arrays of entangled qubits that enable accurate monitoring of all errors in the system, provided the error rate is low. Another crucial requirement is that errors cannot be correlated. Here, we characterize a superconducting multiqubit circuit and find that charge fluctuations are highly correlated on a length scale over 600 µm; moreover, discrete charge jumps are accompanied by a strong transient suppression of qubit energy relaxation time across the millimeter-scale chip. The resulting correlated errors are explained in terms of the charging event and phonon-mediated quasiparticle poisoning associated with absorption of gamma rays and cosmic-ray muons in the qubit substrate. Robust quantum error correction will require the development of mitigation strategies to protect multiqubit arrays from correlated errors due to particle impacts.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
NASA NTRS1994

Universal signal conditioning amplifier

A state-of-the-art instrumentation amplifier capable of being used with most types of transducers has been developed at the Kennedy Space Center. This Universal Signal Conditioning Amplifier (USCA) can eliminate costly measurement setup item and troubleshooting, improve system reliability and provide more accurate data than conventional amplifiers. The USCA can configure itself for maximum resolution and accuracy based on information read from a RAM chip attached to each transducer. Excitation voltages or current are also automatically configured. The amplifier uses both analog and digital state-of-the-art technology with analog-to-digital conversion performed in the early stages in order to minimize errors introduced by offset and gain drifts in the analog components. A dynamic temperature compensation scheme has been designed to achieve and maintain 12-bit accuracy of the amplifier from 0 to 70 C. The digital signal processing section allows the implementation of digital filters up to 511th order. The amplifier can also perform real-time linearizations up to fourth order while processing data at a rate of 23.438 kS/s. Both digital and analog outputs are available from the amplifier.

Medelius, Pedro J.↗
NASA NTRS1999

Low Density Parity Check Codes Based on Finite Geometries: A Rediscovery and More

Low density parity check (LDPC) codes with iterative decoding based on belief propagation achieve astonishing error performance close to Shannon limit. No algebraic or geometric method for constructing these codes has been reported and they are largely generated by computer search. As a result, encoding of long LDPC codes is in general very complex. This paper presents two classes of high rate LDPC codes whose constructions are based on finite Euclidean and projective geometries, respectively. These classes of codes a.re cyclic and have good constraint parameters and minimum distances. Cyclic structure adows the use of linear feedback shift registers for encoding. These finite geometry LDPC codes achieve very good error performance with either soft-decision iterative decoding based on belief propagation or Gallager's hard-decision bit flipping algorithm. These codes can be punctured or extended to obtain other good LDPC codes. A generalization of these codes is also presented.

Kou, Yu↗
NASA NTRS2011

Coding for Parallel Links to Maximize the Expected Value of Decodable Messages

When multiple parallel communication links are available, it is useful to consider link-utilization strategies that provide tradeoffs between reliability and throughput. Interesting cases arise when there are three or more available links. Under the model considered, the links have known probabilities of being in working order, and each link has a known capacity. The sender has a number of messages to send to the receiver. Each message has a size and a value (i.e., a worth or priority). Messages may be divided into pieces arbitrarily, and the value of each piece is proportional to its size. The goal is to choose combinations of messages to send on the links so that the expected value of the messages decodable by the receiver is maximized. There are three parts to the innovation: (1) Applying coding to parallel links under the model; (2) Linear programming formulation for finding the optimal combinations of messages to send on the links; and (3) Algorithms for assisting in finding feasible combinations of messages, as support for the linear programming formulation. There are similarities between this innovation and methods developed in the field of network coding. However, network coding has generally been concerned with either maximizing throughput in a fixed network, or robust communication of a fixed volume of data. In contrast, under this model, the throughput is expected to vary depending on the state of the network. Examples of error-correcting codes that are useful under this model but which are not needed under previous models have been found. This model can represent either a one-shot communication attempt, or a stream of communications. Under the one-shot model, message sizes and link capacities are quantities of information (e.g., measured in bits), while under the communications stream model, message sizes and link capacities are information rates (e.g., measured in bits/second). This work has the potential to increase the value of data returned from spacecraft under certain conditions.

Klimesh, Matthew A.↗
NASA NTRS2005

Highly Reliable, High-Speed, Unidirectional Serial Data Links

Highly reliable, high-speed, unidirectional serial data-communication subsystems have been proposed to be installed in an upgrade of the computing systems aboard the space shuttles. The basic design concept of these serial data links is also adaptable to terrestrial use in applications in which there are requirements for highly reliable serial data communications. The hardware and software aspects of the architecture of the data links are dictated largely by a requirement, in the original space-shuttle application, for one computer to monitor the memory transactions and memory contents of other computers in real time with high reliability and without reliance on requests for retransmission. To minimize weight while affording a capability to transfer data at a required rate of 2.56 x 10(exp 8) bits per second, it was decided that the links would be serial ones of the fiber-channel type. [Fiber channel denotes a type of serial computer bus that is used to connect a computer (usually a supercomputer) with a high-speed data storage device. Depending on the specific application, the physical connection between the transmitter and receiver could be made via an optical fiber or a twisted pair of wires.] Heretofore, fiber-channel links have ordinarily been bidirectional and have operated under protocols that provide for receiving stations to detect errors and request retransmission when necessary. In the present case, the time taken by processing to request retransmission would conflict with the requirement for real-time transfer of data. To ensure reliability without retransmission, a link according to the proposal would utilize a modified version of the normal fiberchannel character set in conjunction with forward error correction by means of a Reed-Solomon code (see figure). The Reed-Solomon encoding and decoding and the translations between the normal and modified character sets would be effected by logic circuitry external to the fiber-channel transmitter and receiver, which would be commercial off-the-shelf units. The receiving end of the link could detect and correct errors at a rate as high as 4 million times per second, if necessary. The receiver detects uncorrectable double-byte errors. It has been estimated that uncorrectable-error rate would amount to one failure in about 10(exp 19) characters.

Cole, Robert M.↗
DOE OSTI2022

Total-Ionizing-Dose Effects on Read Noise of MLC 3-D NAND Memories T

This paper analyzes the total ionizing dose (TID) effects on noise characteristics of commercial multi-level-cell (MLC) 3-D NAND memory technology during the read operation. Additionally, the chips were exposed to a Co-60 gamma-ray source for up to 100 krad(Si) of TID. We find that the number of noisy cells in the irradiated chip increases with TID. Bit-flip noise was more dominant for cells in an erased state during irradiation compared to programmed cells.

3-D NAND Flash↗
DOE OSTI2023

OLCF Summit Supercomputer GPU Snapshots During Double-Bit Errors and Normal Operations

As we move into the exascale era, the power and energy footprints of high-performance computing (HPC) systems have grown significantly larger. Due to the harsh power and thermal conditions the system, components are exposed to extreme operating conditions. Operation of such modern HPC systems requires deep insights into long term system behavior to maintain its efficiency as well as its longevity. To help the HPC community to gain such insights, we provide double-bit errors using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). The dataset relies on Nvidia XID records internally collected by GPU firmware at the time of failure occurrence, on the reboot-time logs of each Summit node, on node-level job scheduler records collected after each job termination, and on a 1Hz data rate from the baseboard management controllers (BMCs) of each Summit compute node using the OpenBMC event subscription protocol. Technical details can be found in the paper Oles et. al “Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study” ICS’24 (https://doi.org/10.1145/3650200.3656615).

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2011

CoNNeCT Baseband Processor Module

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Yamamoto, Clifford K↗