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At least 541 records · Page 30

Total dose effect on soft error rate for dynamic metal-oxide-semiconductor memory cells

A simple model for the soft error rate for dynamic metal-oxide-semiconductor random access memories due to normal galactic radiation was devised and then used to calculate the rate of decrease of the single-event-upset rate with total radiation dose. The computation shows that the decrease in the soft error rate is less than 10 percent per day if the shielding is 0.5 g/sq cm and the spacecraft is in a geosynchronous orbit. The decrease is considerably less in a polar orbiting device.

Benumof, Reuben↗

Harmonic analysis of spacecraft power systems using a personal computer

The effects that nonlinear devices such as ac/dc converters, HVDC transmission links, and motor drives have on spacecraft power systems are discussed. The nonsinusoidal currents, along with the corresponding voltages, are calculated by a harmonic power flow which decouples and solves for each harmonic component individually using an iterative Newton-Raphson algorithm. The sparsity of the harmonic equations and the overall Jacobian matrix is used to an advantage in terms of saving computer memory space and in terms of reducing computation time. The algorithm could also be modified to analyze each harmonic separately instead of all at the same time.

Williamson, Frank↗

Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

Wu, Jiin C.↗

Software for Acquiring Image Data for PIV

PIV Acquisition (PIVACQ) is a computer program for acquisition of data for particle-image velocimetry (PIV). In the PIV system for which PIVACQ was developed, small particles entrained in a flow are illuminated with a sheet of light from a pulsed laser. The illuminated region is monitored by a charge-coupled-device camera that operates in conjunction with a data-acquisition system that includes a frame grabber and a counter-timer board, both installed in a single computer. The camera operates in "frame-straddle" mode where a pair of images can be obtained closely spaced in time (on the order of microseconds). The frame grabber acquires image data from the camera and stores the data in the computer memory. The counter/timer board triggers the camera and synchronizes the pulsing of the laser with acquisition of data from the camera. PIVPROC coordinates all of these functions and provides a graphical user interface, through which the user can control the PIV data-acquisition system. PIVACQ enables the user to acquire a sequence of single-exposure images, display the images, process the images, and then save the images to the computer hard drive. PIVACQ works in conjunction with the PIVPROC program which processes the images of particles into the velocity field in the illuminated plane.

Wernet, Mark P.↗

Microprocessor-to-system/370 interface

The design and operation of a microprocessor interface unit which allows use of a computer terminal for communication at 110 or 300 baud both with a central host computer and with the microprocessor monitor are documented. Additionally, the interface permits the host computer to load the microprocessor memory directly with object code, avoiding the use of intermediate data storage such as paper tape. The central computer, containing an assembler language processor for the target microcomputer, can be used from the terminal with all the flexibility offered by the virtual machine facility, producing object code for the micro plus program listings and supporting outputs. The object code can then be loaded directly to the micro and the same terminal device used to run the micro program, communicating with the micro's monitor routine.

Lilley, R. W.↗

Spacecraft optical disk recorder memory buffer control

This paper discusses the research completed under the NASA-ASEE summer faculty fellowship program. The project involves development of an Application Specific Integrated Circuit (ASIC) to be used as a Memory Buffer Controller (MBC) in the Spacecraft Optical Disk System (SODR). The SODR system has demanding capacity and data rate specifications requiring specialized electronics to meet processing demands. The system is being designed to support Gigabit transfer rates with Terabit storage capability. The complete SODR system is designed to exceed the capability of all existing mass storage systems today. The ASIC development for SODR consist of developing a 144 pin CMOS device to perform format conversion and data buffering. The final simulations of the MBC were completed during this summer's NASA-ASEE fellowship along with design preparations for fabrication to be performed by an ASIC manufacturer.

Hodson, Robert F.↗

1986 Annual Conference on Nuclear and Space Radiation Effects, 23rd, Providence, RI, July 21-23, 1986, Proceedings

The present conference on the effects of nuclear and space radiation on electronic hardware gives attention to topics in the basic mechanisms of radiation effects, dosimetry and energy-dependent effects, electronic device radiation hardness assurance, SOI/SOS radiation effects, spacecraft charging and space radiation, IC radiation effects and hardening, single-event upset (SEU) phenomena and hardening, and EMP/SGEMP/IEMP phenomena. Specific treatments encompass the generation of interface states by ionizing radiation in very thin MOS oxides, the microdosimetry of meson energy deposited on 1-micron sites in Si, total dose radiation and engineering studies, plasma interactions with biased concentrator solar cells, the transient imprint memory effect in MOS memories, mechanisms leading to SEU, and the vaporization and breakdown of thin columns of water.

Ellis, Thomas D.↗

Models and error analyses in urban air quality estimation

Estimation theory has been applied to a wide range of aerospace problems. Application of this expertise outside the aerospace field has been extremely limited, however. This paper describes the use of covariance error analysis techniques in evaluating the accuracy of pollution estimates obtained from a variety of concentration measuring devices. It is shown how existing software developed for aerospace applications can be applied to the estimation of pollution through the processing of measurement types involving a range of spatial and temporal responses. The modeling of pollutant concentration by meandering Gaussian plumes is described in some detail. Time averaged measurements are associated with a model of the average plume, using some of the same state parameters and thus avoiding the problem of state memory. The covariance analysis has been implemented using existing batch estimation software. This usually involves problems in handling dynamic noise; however, the white dynamic noise has been replaced by a band-limited process which can be easily accommodated by the software.

Englar, T., Jr.↗

Method and apparatus for detecting and determining event characteristics with reduced data collection

A method and apparatus for detecting and determining event characteristics such as, for example, the material failure of a component, in a manner which significantly reduces the amount of data collected. A sensor array, including a plurality of individual sensor elements, is coupled to a programmable logic device (PLD) configured to operate in a passive state and an active state. A triggering event is established such that the PLD records information only upon detection of the occurrence of the triggering event which causes a change in state within one or more of the plurality of sensor elements. Upon the occurrence of the triggering event, the change in state of the one or more sensor elements causes the PLD to record in memory which sensor element detected the event and at what time the event was detected. The PLD may be coupled with a computer for subsequent downloading and analysis of the acquired data.

Totman, Peter D.↗

Set processing in a network environment

A combination of a local network, a mass storage system, and an autonomous set processor serving as a data/storage management machine is described. Its characteristics include: content-accessible data bases usable from all connected devices; efficient storage/access of large data bases; simple and direct programming with data manipulation and storage management handled by the set processor; simple data base design and entry from source representation to set processor representation with no predefinition necessary; capability available for user sort/order specification; significant reduction in tape/disk pack storage and mounts; flexible environment that allows upgrading hardware/software configuration without causing major interruptions in service; minimal traffic on data communications network; and improved central memory usage on large processors.

Hardgrave, W. T.↗

High-Performance Spaceflight Computing (HPSC) Middleware Overview

High Performance Spacecraft Computing (HPSC) is a joint project between the National Aeronautics and Space Administration (NASA) and Air Force Research Lab (AFRL) to develop a high-performance multi-core radiation hardened flight processor. HPSC offers a new flight computing architecture to meet the needs of NASA missions through 2030 and beyond. Providing on the order of 100X the computational capacity of current flight processors for the same amount of power, the multicore architecture of the HPSC processor, or "Chiplet" provides unprecedented flexibility in a flight computing system by enabling the operating point to be set dynamically, trading among needs for computational performance, energy management and fault tolerance. The HPSC Chiplet is being developed by Boeing under contract to NASA, and is expected to provide prototypes in 2021. The HPSC Chiplet prototypes will be delivered with an evaluation board, system emulators, comprehensive system software, and a software development kit. In addition to the vendor deliverables, the AFRL is funding the development of a flexible Middleware to be developed by NASA Jet Propulsion Laboratory and NASA Goddard Space Flight Center. The HPSC Middleware provides a suite of thirteen high level services to manage the compute, memory and I/O resources of this complex device.This presentation will provide an overview of the HPSC project, including a hardware overview, system software overview, Middleware overview, and mission use cases. The hardware overview will provide a look at the 8 core High Performance Processing Subsystem (HPPS), the Real Time Processing Subsystem (RTPS), the Chiplet Configuration Management Subsystem, on chip peripherals, and high speed I/O. The system software overview will introduce the boot loaders, operating systems, device drivers, and software development environment. The Middleware overview will provide insight into the high-level services that will be provided to help mission developers manage the many resources and configurations made possible with the Chiplet. Finally, the presentation will provide a brief look at the mission use cases that can be enabled with this next generation architecture.

middleware↗

Monitoring Composite Material Pressure Vessels with a Fiber-Optic/Microelectronic Sensor System

We discuss the concept of an integrated, fiber-optic/microelectronic distributed sensor system that can monitor composite material pressure vessels for Air Force space systems to provide assessments of the overall health and integrity of the vessel throughout its entire operating history from birth to end of life. The fiber optic component would include either a semiconductor light emitting diode or diode laser and a multiplexed fiber optic sensing network incorporating Bragg grating sensors capable of detecting internal temperature and strain. The microelectronic components include a power source, a pulsed laser driver, time domain data acquisition hardware, a microprocessor, a data storage device, and a communication interface. The sensing system would be incorporated within the composite during its manufacture. The microelectronic data acquisition and logging system would record the environmental conditions to which the vessel has been subjected to during its storage and transit, e.g., the history of thermal excursions, pressure loading data, the occurrence of mechanical impacts, the presence of changing internal strain due to aging, delamination, material decomposition, etc. Data would be maintained din non-volatile memory for subsequent readout through a microcomputer interface.

Klimcak, C.↗

Development of a high-speed H-alpha camera system for the observation of rapid fluctuations in solar flares

A solid-state digital camera was developed for obtaining H alpha images of solar flares with 0.1 s time resolution. Beginning in the summer of 1988, this system will be operated in conjunction with SMM's hard X-ray burst spectrometer (HXRBS). Important electron time-of-flight effects that are crucial for determining the flare energy release processes should be detectable with these combined H alpha and hard X-ray observations. Charge-injection device (CID) cameras provide 128 x 128 pixel images simultaneously in the H alpha blue wing, line center, and red wing, or other wavelength of interest. The data recording system employs a microprocessor-controlled, electronic interface between each camera and a digital processor board that encodes the data into a serial bitstream for continuous recording by a standard video cassette recorder. Only a small fraction of the data will be permanently archived through utilization of a direct memory access interface onto a VAX-750 computer. In addition to correlations with hard X-ray data, observations from the high speed H alpha camera will also be correlated and optical and microwave data and data from future MAX 1991 campaigns. Whether the recorded optical flashes are simultaneous with X-ray peaks to within 0.1 s, are delayed by tenths of seconds or are even undetectable, the results will have implications on the validity of both thermal and nonthermal models of hard X-ray production.

Kiplinger, Alan L.↗

Effects of space radiation on electronic microcircuits

The single event effects or phenomena (SEP), which so far have been observed as events falling on one or another of the SE classes: Single Event Upset (SEU), Single Event Latchup (SEL) and Single Event Burnout (SEB), are examined. Single event upset is defined as a lasting, reversible change in the state of a multistable (usually bistable) electronic circuit such as a flip-flop or latch. In a computer memory, SEUs manifest themselves as unexplained bit flips. Since latchup is in general caused by a single event of short duration, the single event part of the SEL term is superfluous. Nevertheless, it is used customarily to differentiate latchup due to a single heavy charged particle striking a sensitive cell from more ordinary kinds of latchup. Single event burnout (SEB) refers usually to total instantaneous failure of a power FET when struck by a single particle, with the device shorting out the power supply. An unforeseen failure of these kinds can be catastrophic to a space mission, and the possibilities are discussed.

Kolasinski, W. A.↗

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

Phillips, Thomas A.↗

Delay Tolerant, Radio Frequency Identification (RFID )-enabled Sensing

Radio Frequency Identification (RFID) technology offers a completely passive method to transmit fixed data sequences from an RFID tag, which typically doesn’t have its own power supply, to an interrogator. Radio frequency (RF) energy harvested from the interrogator is rectified by the tag and used to charge an integrated circuit (IC). The IC then modulates the received signal with the data stored on the tag and reflects the energy back to the interrogator. RFID has seen great proliferation in terrestrial inventory management applications, and it has recently made the jump to spaceflight applications onboard the International Space Station, augmenting an existing optical bar‐code infrastructure for tracking supplies. A number of advanced automated logistics management (ALM) concepts employing RFID are currently being developed and evaluated, including so‐called “smart” shelves, cubbies, and trash receptacles using low‐power, embeddable RFID interrogators. An infrastructure where both crew members and robotic assistants, such as autonomous free flyers, are similarly equipped with small RFID interrogators seems likely. It therefore behooves us to consider extending this infrastructure beyond ALM to applications such as low power, embedded sensing. Typically, data on an RFID tag can only be written by an RFID interrogator, using interrogator energy. In recent years, however, a few efforts have focused on using that energy to drive data acquisition from the tag IC, allowing the tag to modify its stored data sequence with sensor data before replying to an interrogator. In this way, the tag can act as a completely passive sensing device. One problem exists with this approach, however: the tag cannot gather data when an interrogator is not present. Thus, strictly passive RFID sensing tags cannot gather data at regular intervals, in the manner of a typical wireless sensor network, without careful, and impractical, planning of mobile interrogator movements. To address this shortcoming, we look to a recent advance in RFID technology which allows an external microprocessor to power the tag IC and write directly into its RFID memory using a wired serial interface. In this paradigm, data gathering is driven by a small, on‐board power supply (using batteries or harvested energy), and data transfer is provided passively through the RFID interrogation service. Since communication typically consumes the lion’s share of power in WSNs, such a technique has the potential to enable extremely long‐lived, embedded wireless sensing when used with extremely low‐current microcontrollers. Since the communication channel is only open when an interrogator is present and actively interrogating the RFID sensing tag, transport of periodically‐sampled sensor data presents itself as a delay/disruption‐tolerant networking (DTN) problem. In this paper, we present the design of a DTN‐like overlay on the common EPC Global, Class 1, Generation 2 RFID standard. This overlay allows seamless, guaranteed data transfer using the EPC Global protocol, supporting extremely low‐power, embedded sensing using an infrastructure likely to be already in place for ALM applications. We evaluate a prototype implementation of a complete end‐to‐end system using a robotic RFID interrogation agent, and we present future directions for the development of this sensing technique.

Raymond S. Wagner↗

Implementation of real-time digital signal processing systems

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct implementation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

Narasimha, M.↗

Fabrication system, method and apparatus for microelectromechanical devices

A fabrication system and method of fabrication for producing microelectromechanical devices such as field-effect displays using thin-film technology. A spacer is carried at its proximal end on the surface of a substrate having field-effect emitters with the spacer being enabled for tilting movement from a nested position to a deployed position which is orthogonal to the plane of the substrate. An actuator is formed with one end connected with the substrate and another end connected with spacer. The actuator is made of a shape memory alloy material which contracts when heated through the material's phase-change transition temperature. Contraction of the actuator exerts a pulling force on the spacer which is tilted to the deployed position. A plurality of the spacers are distributed over the area of the display. A glass plate having a phosphor-coated surface is fitted over the distal ends of the deployed spacer.

Johnson, A. David↗