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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Remotely controllable actuating device

An actuating device can change a position of an active member that remains in substantially the same position in the absence of a force of a predetermined magnitude on the active member. The actuating device comprises a shape-memory alloy actuating member for exerting a force when actuated by changing the temperature thereof, which shape-memory alloy actuating member has a portion for connection to the active member for exerting thereon a force having a magnitude at least as large as the predetermined magnitude for moving the active member to a desired position. Actuation circuitry is provided for actuating the shape-memory alloy actuating member by changing the temperature thereof only for the time necessary to move the active member to the desired position. The invention is particularly useful for changing the position of a camber-adjusting tab on a helicopter rotor blade by using two shape-memory alloy members that can act against each other to adjust dynamic properties of the rotor blade as it is rotating.

McKillip, Jr., Robert M.↗
NASA NTRS2012

Goldstone Solar System Radar Waveform Generator

Due to distances and relative motions among the transmitter, target object, and receiver, the time-base between any transmitted and received signal will undergo distortion. Pre-distortion of the transmitted signal to compensate for this time-base distortion allows reception of an undistorted signal. In most radar applications, an arbitrary waveform generator (AWG) would be used to store the pre-calculated waveform and then play back this waveform during transmission. The Goldstone Solar System Radar (GSSR), however, has transmission durations that exceed the available memory storage of such a device. A waveform generator capable of real-time pre-distortion of a radar waveform to a given time-base distortion function is needed. To pre-distort the transmitted signal, both the baseband radar waveform and the RF carrier must be modified. In the GSSR, this occurs at the up-conversion mixing stage to an intermediate frequency (IF). A programmable oscillator (PO) is used to generate the IF along with a time-varying phase component that matches the time-base distortion of the RF carrier. This serves as the IF input to the waveform generator where it is mixed with a baseband radar waveform whose time-base has been distorted to match the given time-base distortion function producing the modulated IF output. An error control feedback loop is used to precisely control the time-base distortion of the baseband waveform, allowing its real-time generation. The waveform generator produces IF modulated radar waveforms whose time-base has been pre-distorted to match a given arbitrary function. The following waveforms are supported: continuous wave (CW), frequency hopped (FH), binary phase code (BPC), and linear frequency modulation (LFM). The waveform generator takes as input an IF with a time varying phase component that matches the time-base distortion of the carrier. The waveform generator supports interconnection with deep-space network (DSN) timing and frequency standards, and is controlled through a 1 Gb/s Ethernet UDP/IP interface. This real-time generation of a timebase distorted radar waveform for continuous transmission in a planetary radar is a unique capability.

Quirk, Kevin J.↗
NASA NTRS2020

Avalanche ASV016204 (Pre-Production Samples) 40nm MRAM Total Ionizing Dose Test Report

The purpose of this test was to characterize the Avalanche Technology ASV016204’s total dose response. In the test, the device was exposed to high dose rate (HDR) irradiations using gamma radiation. Device functionality (in terms of memory cell upsets and read/write ability) as well as power supply currents during various modes of operations were recorded.

Total Ionizing Dose (TID)↗
DOE OSTI2020

Device and method for cache utilization aware data compression

A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.

Das, Shomit N.↗
DOE OSTI2022

Scalable Al 2 O 3 –TiO 2 Conductive Oxide Interfaces as Defect Reservoirs for Resistive Switching Devices

Abstract Resistive switching devices herald a transformative technology for memory and computation, offering considerable advantages in performance and energy efficiency. Here, a simple and scalable material system of conductive oxide interfaces is employed, and their unique properties are leveraged for a new type of resistive switching device. An Al 2 O 3 –TiO 2 ‐based valence‐change resistive switching device, where the conductive oxide interface serves both as the bottom electrode and as a reservoir of defects for switching, is demonstrated. The amorphous–polycrystalline Al 2 O 3 –TiO 2 conductive interface is obtained following the technological path of simplifying the fabrication of the 2D electron gases (2DEGs), making them scalable for practical mass integration. Physical analysis of the device chemistry and microstructure with comprehensive electrical analysis of its switching behavior and performance is combined. The origin of the resistive switching is pinpointed to the conductive oxide interface, which serves both as the bottom electrode and as a reservoir of oxygen vacancies. The latter plays a key role in valence‐change resistive switching devices. The new device, based on scalable and complementary metal–oxide–semiconductor (CMOS)‐technology‐compatible fabrication processes, opens new design spaces toward increased tunability and simplification of the device selection challenge.

36 MATERIALS SCIENCE↗
NASA NTRS1984

Operating systems

A counter operating system creates a hierarchy of levels of abstraction, so that at a given level all details concerning lower levels can be ignored. This hierarchical structure separates functions according to their complexity, characteristic time scale, and level of abstraction. The lowest levels include the system's hardware; concepts associated explicitly with the coordination of multiple tasks appear at intermediate levels, which conduct 'primitive processes'. Software semaphore is the mechanism controlling primitive processes that must be synchronized. At higher levels lie, in rising order, the access to the secondary storage devices of a particular machine, a 'virtual memory' scheme for managing the main and secondary memories, communication between processes by way of a mechanism called a 'pipe', access to external input and output devices, and a hierarchy of directories cataloguing the hardware and software objects to which access must be controlled.

Denning, P. J.↗
DOE OSTI2025

SULI Deliverables Using: Python-B1500 [Slides]

A new electrical setup for testing ECRAM devices is described in this presentation. This presentation details the background of ECRAM devices, how the B1500 is used to program ECRAM devices, and the python GUI that was created for controlling the B1500. ECRAM devices are a form of non-volatile memory. The stored data is the resistance between two of the terminals on the device. Using only the B1500, the ECRAM devices can be programmed and the state read out. This creates a simple, logical testing setup. The overall setup was successful, ECRAM devices could easily be programmed and measured. However, there is still room for improvement. Specifically, in the creation of an automated “Program” feature and a “Data Collection” feature. These features will require additional advances in the understanding of ECRAM devices but will greatly automate and improve the current data collection and application of ECRAM devices.

42 ENGINEERING↗
DOE OSTI2020

Understanding the Impact of Memory Access Patterns in Intel Processors

Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.

Alaul haque monil, Mohammad↗
NASA NTRS2011

AC Electric Field Activated Shape Memory Polymer Composite

Shape memory materials have drawn interest for applications like intelligent medical devices, deployable space structures and morphing structures. Compared to other shape memory materials like shape memory alloys (SMAs) or shape memory ceramics (SMCs), shape memory polymers (SMPs) have high elastic deformation that is amenable to tailored of mechanical properties, have lower density, and are easily processed. However, SMPs have low recovery stress and long response times. A new shape memory thermosetting polymer nanocomposite (LaRC-SMPC) was synthesized with conductive fillers to enhance its thermo-mechanical characteristics. A new composition of shape memory thermosetting polymer nanocomposite (LaRC-SMPC) was synthesized with conductive functionalized graphene sheets (FGS) to enhance its thermo-mechanical characteristics. The elastic modulus of LaRC-SMPC is approximately 2.7 GPa at room temperature and 4.3 MPa above its glass transition temperature. Conductive FGSs-doped LaRC-SMPC exhibited higher conductivity compared to pristine LaRC SMP. Applying an electric field at between 0.1 Hz and 1 kHz induced faster heating to activate the LaRC-SMPC s shape memory effect relative to applying DC electric field or AC electric field at frequencies exceeding1 kHz.

Kang, Jin Ho↗
NASA NTRSDate not supplied

Design and Analysis of Shape Memory Spring Tires for Martian and Lunar Rover Vehicles

Shape memory alloys (SMAs) have played an important role in various innovative engineering and medical applications, such as aerospace actuators, vibration damping devices, and coronary stents. In applications, shape memory alloys are commonly utilized in two fundamentally different ways: (i) making use of the superelasticity/ pseudoelasticity (SE/PE) phenomena, as in applications in biomedical engineering, and (ii) taking advantages of the shape memory effect (SME), as is used for actuators. Their ability to act in such vastly different capacities is mainly due to their unique capability to recover large amounts of deformation produced by either applied stresses or temperature changes. One recent emerging application in use of SMAs has been in the area of non-pneumatic tire designs for Martian or Lunar roving vehicles. These vehicles require tires that are capable of traversing rugged terrain while withstanding extreme temperatures and atmospheric conditions. Inspired by the flexible wire mesh tires used on three Lunar Roving Vehicle (LRV) missions to the Moon on Apollo 15, 16, and 17, a new compliant tire technology was developed by the NASA Glenn Research Center (GRC) and Goodyear Tire & Rubber, known as the Spring Tire. The Spring Tire consists of several hundred coiled springs woven into a flexible mesh and formed into the shape of a tire. Like the LRV wire mesh tires, the original Spring Tires were made from spring steel and were prone to permanent deformation when undergoing high localized loads. Later, a new iteration of this technology was invented, known as the ‘Superelastic Tire’. This new technology incorporated the use of superelastic SMA springs, which could effectively undergo approximately 30 times more reversible deformation than the steel spring. It also provided even greater durability and allowed for more flexibility in design, such as the use of other structural forms to reduce mass or increase load carrying capacity. Because of the unique nature of both the SMA material and the complex interactions between the springs, designing Spring Tires for a specific application requires extensive effort. Historically, design decisions have relied on full-scale empirical testing; however, this is very expensive and time consuming, especially when multiple iterations are needed. Therefore, developing a large-scale, robust, and predictive numerical model entailing complex spring interactions and the shape memory material behavior within a tire construct is the first essential step towards a successful design program. The current work focuses on implementation of the user-defined Shape Memory Alloy (SMA) model, otherwise known as SMA-GVIPs, in the Finite Element analysis (FEA) program ABAQUS for large-scale simulations of the GRC-developed Spring Tires made of SMA. The novelty of this work lies in the thorough, detail-oriented, and computationally efficient finite element analysis of full-scale SMA tires. A well-thought material characterization plan followed by model validation and a systemic sensitivity study on SMA tires has never been reported in the previous literature. The main objective of this study is to help the team improve and optimize the structural design of the SMA tires through in-depth numerical analysis and sensitivity studies. Various design variables (wire diameter, coil diameter, pitch, bead angle, and number of springs) were varied to study their influence on the global load-displacement response of the tire construct. A detailed investigation of the three-dimensional stress states was also carried out to enhance our understanding of the local changes as the tire goes through global deformation. It was concluded that a robust numerical model with a good predictive capability, together with a thoughtfully crafted sensitivity study can result in improved design iterations required to reach a desired tire performance while, significantly reducing manufacturing, labor and testing expenses. A summary of the Finite Element (FE) model construction will be presented together with a description of the user-defined SMA model, characterization process, experimental results, model validation, and numerical sensitivity study results.

shape memory alloys↗
DOE OSTI2021

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. Further, the different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

36 MATERIALS SCIENCE↗
NASA NTRS2004

Single Event Effects in Highly Scaled Devices for Space Applications

This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.

microelectronics↗
NASA NTRS2011

Characterization of an Autonomous Non-Volatile Ferroelectric Memory Latch

We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

John, Caroline S.↗
NASA NTRS1992

Development of A Non-Explosive Release Device for Aerospace Applications

A simple, non-explosive, high load-capacity release mechanism using shape memory alloy is currently being developed for space flight. This device, the Frangibolt, could replace most pyrotechnic devices in applications where the need for safety, reliability, non-destructive testing, and minimal mechanical shock is more crucial than the need for rapid actuation. Prototype hardware has been designed, tested, and proven in laboratory conditions. Operation and demonstration of these devices evidenced reliable and repeatable performance, clearly indicating that extensive testing for flight qualification is warranted. Here, the Frangibolt design is discussed, recent test results of laboratory units are described, and the work that must be performed in the upcoming months to qualify the device for aerospace applications is addressed.

John D Busch↗
DOE OSTI2023

Towards generic memory forensic framework for programmable logic controllers

A Programmable Logic Controller (PLC) is a microprocessor-based controller that is used to automate physical processes in critical infrastructure and various other industries and manufacturing sectors. Initially, PLCs were completely isolated from the Internet, and cyber security was not incorporated at the time of development. The introduction of industry 4.0 and the evolution of ICS systems to communicate over public IP addresses from the Internet enhanced productivity and efficiency, but Internet connectivity exposed the systems and their vulnerabilities, which led to an increase in cyber attacks. When a system is sabotaged/compromised, security analysts need to get to the root cause of the attack as quickly as possible to recover the system. To do so, memory forensic analysis is critical to provide a unique insight into the run-time memory activities and extract a reliable source of evidence. In this paper, we analyze the memory structure of the Schneider Electric Modicon M221 PLC. To build a memory profile, we reverse engineer the communication protocol and conduct differential analysis to gain knowledge about the structure of the memory and the low-level representation of control logic instructions. We then identify dynamic and static memory regions by modifying different project fields and conducting differential analysis, which allows us to identify boundaries of critical memory structures and extract important forensic artifacts that can be found in the memory. The Python implementation of the memory profile can help reduce the time and effort required for manual analysis in case of cyber incident or system failure.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
NASA NTRS2008

Are Current SEE Test Procedures Adequate for Modern Devices and Electronics Technologies?

Believe it or not, this has been a simplistic look at starting a checklist for SEE testing. Given a memory that has 68 operating modes, when a SEU occurs that changes the mode, just how do you determine what's going on? Laser and microbeam tests can help, but not easily for modern packaged devices. Expanding this approach to other more complex devices such as ADCs or processors as well as analog devices should be considered. The recommendation is to use the existing text standards as the starting point. Just make your own checklist for the device/technology/issues being considered. At HEART 2007, we presented some of the burgeoning challenges associated with single event effect(SEE) testing of modern commercial memories: a) Package, device complexity, test fixture, and data analysis issues were discussed; b) "Complete" SEE Characterization would take 15 years; c) Qualification test costs have a greater than 4 times increase over the last decade. In this talk, we continue to explore the roles of technology with an emphasis on the existing SEE Test Procedures and some of the concerns related to modern devices. The primary objective of the briefing is to provide some overarching guidance concerning the many considerations involved in the formulation of a SEE test plan provided in a " Checklist" format.we note that there is no such thing as a complete check list and that the best approach is to develop a flexible test plan that takes into account the device type and functions, the device technology, circuit and package design, and, of course, test facility and beam characteristics.

LaBel, Kenneth A.↗
NASA NTRS1980

A spacecraft mass memory design using self-structured magnetic bubbles

A self-structured multilayered bubble device developed for spacecraft sensor systems is described. The data link buffer mass memory is analyzed, and system characteristics are estimated based on a nominal 1.6 micron bubble diameter. It is shown that a memory of at least 10 billion bits capacity and 30 megabits per second could be developed with conventional spacecraft constraints.

Stermer, R. L., Jr.↗