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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
NASA NTRS2010

A Data Filter for Identifying Steady-State Operating Points in Engine Flight Data for Condition Monitoring Applications

This paper presents an algorithm that automatically identifies and extracts steady-state engine operating points from engine flight data. It calculates the mean and standard deviation of select parameters contained in the incoming flight data stream. If the standard deviation of the data falls below defined constraints, the engine is assumed to be at a steady-state operating point, and the mean measurement data at that point are archived for subsequent condition monitoring purposes. The fundamental design of the steady-state data filter is completely generic and applicable for any dynamic system. Additional domain-specific logic constraints are applied to reduce data outliers and variance within the collected steady-state data. The filter is designed for on-line real-time processing of streaming data as opposed to post-processing of the data in batch mode. Results of applying the steady-state data filter to recorded helicopter engine flight data are shown, demonstrating its utility for engine condition monitoring applications.

Simon, Donald L.↗
DOE OSTI2023

Oak Ridge National Laboratory Security by Design: A Plant Design and Component-Based Approach to Technical Solutions to Insider and Outsider Threat

Security costs for nuclear reactors have been shown to rise over the lifecycle of a nuclear facility as new threats, security weaknesses, and the generic threat profile of the plant location change over time. This paper conducts a review of the technological gaps that currently exist in Security by Design (SeBD) based on the literature available and attempts to close those gaps through proposing technological constructs and processes that can integrate safety and security in the design process of a plant, with a primary focus on SMR technology. Under the new modular and mass manufacturing regime, where plant designs attempt to reduce costs with potential economies of scale and modular construction, the current SeBD definitions focusing on state level regulators are not considered adequate since the licensing stage is often too late in the design process to integrate the true cost savings of SeBD. Thus, this paper attempts to remedy the current logic in order to allow for continuous implementation of security alongside the development of the safety concept for the plant. If adopted within the design process the establishment of this type of technology will allow for a technological ecosystem to evolve that will imbed security concepts into the physical design of the components of the plant.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
NASA NTRS1995

Advanced control design for hybrid turboelectric vehicle

The new environment standards are a challenge and opportunity for industry and government who manufacture and operate urban mass transient vehicles. A research investigation to provide control scheme for efficient power management of the vehicle is in progress. Different design requirements using functional analysis and trade studies of alternate power sources and controls have been performed. The design issues include portability, weight and emission/fuel efficiency of induction motor, permanent magnet and battery. A strategic design scheme to manage power requirements using advanced control systems is presented. It exploits fuzzy logic, technology and rule based decision support scheme. The benefits of our study will enhance the economic and technical feasibility of technological needs to provide low emission/fuel efficient urban mass transit bus. The design team includes undergraduate researchers in our department. Sample results using NASA HTEV simulation tool are presented.

Abban, Joseph↗
NASA NTRS2012

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir↗
DOE OSTI2025

Three-Dimensional Bubble Fluidics in Architected Porous Media

Gas bubble flows in porous media often exhibit complex and seemingly unpredictable behaviors that are difficult to control. This lack of control limits the ability to design effective devices which manage multiphase flows. Here, we show how the design of 3D printed pores can deterministically control the flow path of an injected gas stream. Open cell structures can be designed to shape the gas/liquid interface with fidelity to control how the two phases are distributed throughout a porous material. The distributed gas volume is free to interact physically and chemically with the surrounding liquid phase, an effect we exploit to create a logical control gate to redirect flows within a lattice. This also allows us to design architectures for reactive capture and aerating bioreactors, resulting in patterned boundaries which can make more effective use of the liquid and gas reagents.

3D microfluidics↗
DOE OSTI2024

LENS: Learning Enabled Network Synthesis

RTRC and UMD have developed novel machine learning based methods under the ARPA-E DIFFERENTIATE program for rapid acceleration of hypothesis generation in complex architecture design spaces involving both discrete choices of component inclusion and interconnection and continuous parametric decisions. The project named Learning Enabled Network Synthesis (LENS) further demonstrated the developed methods on challenging electrical power converter design problems by identifying the most suitable circuit topologies and simultaneously selecting the most appropriate components to achieve optimized design of power converter with improved performances. We demonstrated that LENS could enable exploration of very large design space of circuit topologies and components by addressing the limitations of conventional design process in non-linear, high switching speed, multi-dimensional power converter design and optimization. The key innovation developed in LENS is the seamless integration of statistical learning and logical reasoning techniques and building on the individual strengths of these techniques for rapid hypothesis discovery. The main component of LENS comprises of: 1) Graph Reasoning Engine (GRE) to enforce composition rules that rapidly reject all discrete architectures that are composed incorrectly and generates an adaptive database of feasible designs which can be used by ML modules, 2) Graph Generative Learning module which is a deep neural network based generative model for graph architectures which can enable design space exploration beyond the dataset generated by the GRE, 3) Graph Reduced Order Model (ROM) for graph domains for accelerating computation of output metrics, and 4) Active learning and Rule Discovery module for sample efficient learning and extracting logical rules from the learned ML models which will be integrated in the GRE to enhance the filtering effectiveness. LENS approach can be applied to any design domains where designs can be represented as multi-attribute graphs. The LENS team integrated the various technical innovations listed above into an optimization pipeline and exercised the optimization pipeline on the converter design problem. The LENS project demonstrated that the developed AI/ML technologies can be used to generate novel converter circuits >45x faster than experts on chosen use-cases. This can enable faster design space exploration and identification of new designs which are not considered by experts due to the increasing design space complexity. This has significant potential impact on the public and energy needs of the country. It is currently estimated that 30% of all electrical powers generated passes through power converters. The future estimate is that 80% of all power generated would be passing through converters. LENS fills a critical gap in this space since by accelerating the design process the designers would be able to generate more efficient converters which can lead to significant energy savings for the country.

42 ENGINEERING↗
NASA NTRS1993

Mission Design For the Mars Environmental Survey

The Mars Environmental Survey (MESUR) mission is the next logical evolutionary step in the thirty year program of Mars exploration. The purpose of this mission is to perform long duration in situ scientific measurements of the Martian environment at a number of globally distributed sites.

Mars↗
NASA NTRS1979

NASF transposition network: A computing network for unscrambling p-ordered vectors

The viewpoints of design, programming, and application of the transportation network (TN) is presented. The TN is a programmable combinational logic network that connects 521 memory modules to 512 processors. The unscrambling of p-ordered vectors to 1-ordered vectors in one cycle is described. The TN design is based upon the concept of cyclic groups from abstract algebra and primitive roots and indices from number theory. The programming of the TN is very simple, requiring only 20 bits: 10 bits for offset control and 10 bits for barrel switch shift control. This simple control is executed by the control unit (CU), not the processors. Any memory access by a processor must be coordinated with the CU and wait for all other processors to come to a synchronization point. These wait and synchronization events can be a degradation in performance to a computation. The TN application is for multidimensional data manipulation, matrix processing, and data sorting, and can also perform a perfect shuffle. Unlike other more complicated and powerful permutation networks, the TN cannot, if possible at all, unscramble non-p-ordered vectors in one cycle.

Lim, R. S.↗
NASA NTRS2003

Silicon validation of evolution-designed circuits

This paper is the first to report on a silicon implementation of circutis evolved in simulation. Several circuits were evolved an fabricated in 0.5 micron CMOS process; this paper focuses on results of logical gates evolved at transistor level. It discusses the steps taken in order to increase the chances of robust and portable designs, summarizes the results of characterization tests based on chip measurements, and comments on the performance comparing to simulations.

evolutionary algorithms↗
DOE OSTI2022

All‐Polymer Bulk‐Heterojunction Organic Electrochemical Transistors with Balanced Ionic and Electronic Transport

Abstract The rapid development of organic electrochemical transistor (OECTs)‐based circuits brings new opportunities for next‐generation integrated bioelectronics. The all‐polymer bulk‐heterojunction (BHJ) offers an attractive, inexpensive alternative to achieve efficient ambipolar OECTs, and building blocks of logic circuits constructed from them, but have not been investigated to date. Here, the first all‐polymer BHJ‐based OECTs are reported, consisting of a blend of new p‐type ladder conjugated polymer and a state‐of‐the‐art n‐type ladder polymer. The whole ladder‐type polymer BHJ also proves that side chains are not necessary for good ion transport. Instead, the polymer nanostructures play a critical role in the ion penetration and transportation and thus in the device performance. It also provides a facile strategy and simplifies the fabrication process, forgoing the need to pattern multiple active layers. In addition, the development of complementary metal–oxide–semiconductor (CMOS)‐like OECTs allows the pursuit of advanced functional logic circuitry, including inverters and NAND gates, as well as for amplifying electrophysiology signals. This work opens a new approach to the design of new materials for OECTs and will contribute to the development of organic heterojunctions for ambipolar OECTs toward high‐performing logic circuits.

Chemistry↗
NASA NTRSDate not supplied

Lessons Learned from NASA Goddard Space Flight Center’s Product Development Lead Training Schedule and Cost Development Workshop: Continuous Improvement

This presentation provides a status of the Goddard Space Flight Center (GSFC) effort to increase foundational knowledge of Product Development Leads (PDLs) in schedule and cost management including earned value management (EVM). In 2012, GSFC’s Engineering and Technology Directorate (ETD) implemented an in-house training program to prepare PDLs for managing the technical, cost, schedule, and risk aspects of spaceflight systems to meet their subsystem commitments. Developed in-house, the PDL training program provides an integrated approach to requirements development, risk, schedule and cost management, EVM, performance tracking, and other areas. The program has been held twice yearly since its inception with 531 participating and 451 completing the curriculum. In 2017, the program won the Robert H. Goddard award for Quality and Process Improvement. Program development and evolution were presented in the 2018 NASA Schedule and Cost Symposium. The presentation was so well received that this year we focus on one workshop within the program: Schedule and Cost Development, including EVM. We examine the on-going logic modeling process and how participant and stakeholder data influence workshop content and design, and how the disciplines of schedule and cost contribute to mission success. In this presentation we refresh you on how the approach integrates lecture, small group discussion, estimating, case study exercises, and problem solving. We update you on the data collected from participants and stakeholders, and we discuss how we use these data to measure training effectiveness. Specific topics include: • How the logic model is used as the backbone for continuous program improvement, • How feedback influences implementation and curriculum updates, • How data collection and analysis inform workshop content and development, including participant discoveries of EVM data, • How including the resource analyst and planner in the product development team supports project success.

Lessons Learned↗
DOE OSTI2020

Genetic circuit characterization by inferring RNA polymerase movement and ribosome usage

To perform their computational function, genetic circuits change states through a symphony of genetic parts that turn regulator expression on and off. Debugging is frustrated by an inability to characterize parts in the context of the circuit and identify the origins of failures. Here, we take snapshots of a large genetic circuit in different states: RNA-seq is used to visualize circuit function as a changing pattern of RNA polymerase (RNAP) flux along the DNA. Together with ribosome profiling, all 54 genetic parts (promoters, ribozymes, RBSs, terminators) are parameterized and used to inform a mathematical model that can predict circuit performance, dynamics, and robustness. The circuit behaves as designed; however, it is riddled with genetic errors, including cryptic sense/antisense promoters and translation, attenuation, incorrect start codons, and a failed gate. While not impacting the expected Boolean logic, they reduce the prediction accuracy and could lead to failures when the parts are used in other designs. Finally, the cellular power (RNAP and ribosome usage) required to maintain a circuit state is calculated. This work demonstrates the use of a small number of measurements to fully parameterize a regulatory circuit and quantify its impact on host.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2023

Better Than Worst-Case Decoding for Quantum Error Correction

The overheads of classical decoding for quantum error correction in cryogenic quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottlenecked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case (over 90% of the time), error correction 'syndromes' are fairly trivial with high redundancy / sparsity, since the error correction codes are over-provisioned to be able to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial scenarios can be handled with insignificant overhead, thereby alleviating any bottlenecks towards handling the worst-case scenarios by state-of-the-art means. Here, we propose Better Than Worst-Case Decoding for Quantum Error Correction, targeting cryogenic quantum systems and Surface Code, consisting of: On-chip Clique Decoder: An extremely lightweight decoder for correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented and evaluated for SFQ logic. Statistical Off-chip Bandwidth Allocation: A statistical confidence-based technique for allocation of off-chip decoding bandwidth, to efficiently handle the rare complex decodes that are not covered by the Clique Decoder. Decode-Overflow Execution Stalling: A method to stall circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, BTWC decoding achieves 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of a state-of-the-art off-chip decoder. Further, it achieves 10-1000x bandwidth reduction over prior bandwidth reduction techniques, as well as 15-37x resource overhead reduction compared to prior on-chip decoding.

cryogenic optimization↗
DOE OSTI2021

A-SST Initial Specification

The U.S. Army Research Office (ARO), in partnership with IARPA, are investigating innovative, efficient, and scalable computer architectures that are capable of executing next-generation large scale data-analytic applications. These applications are increasingly sparse, unstructured, non-local, and heterogeneous. Under the Advanced Graphic Intelligence Logical computing Environment (AGILE) program, Performer teams will be asked to design computer architectures to meet the future needs of the DoD and the Intelligence Community (IC). This design effort will require flexible, scalable, and detailed simulation to assess the performance, efficiency, and validity of their designs. To support AGILE, Sandia National Labs will be providing the AGILE-enhanced Structural Simulation Toolkit (A-SST). This toolkit is a computer architecture simulation framework designed to support fast, parallel, and multi-scale simulation of novel architectures. This document describes the A-SST framework, some of its library of simulation models, and how it may be used by AGILE Performers.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

FEM Analysis of Hybrid LTS/HTS Cos-Theta Dipole Magnet

After the recent results on Bi-2212 superconductive magnets realized and tested in canted cosine-theta and solenoid designs, respectively, at Lawrence Berkeley National Laboratory (LBNL) and NHMFL, the first Bi-2212 stress-managed cosine-theta insert magnet is in the assembly phase at Fermilab. This insert will be part of the first hybrid cosine-theta magnet made of Nb3Sn outer layers within the US-MDP effort to reach 20 T bore field. This paper reports the analytical analysis of the cosine-theta Nb3Sn/Bi-2212 hybrid magnet. As an introduction, it shows the validation of the finalized HTS coils' design optimized using the ROXIE code. Subsequently, it reports the parameters, logic, and implementation method of the 2D electromagnetic and mechanical FEM analysis of the LTS/HTS hybrid magnet. Results from the ANSYS detailed model made with sub-modeling geometry are compared with the homogeneous model implemented in the past. Moreover, a Python code was implemented to simulate the current degradation due to stresses in the detail-modeled conductor areas. The current degradation is introduced in the simulation dynamics for both conductors as an iteration process during the energization load step only after applying pre-stress and thermal loads. The numerical and graphic results of the 2D cosine-theta LTS/HTS magnet cross-section will be described and analyzed.

D'Agliano, A.↗
DOE OSTI2025

An Experiment with LLMs as Database Design Tutors: Persistent Equity and Fairness Challenges in Online Learning

As large language models (LLMs) continue to evolve, their capacity to replace humans as their surrogates is also improving. As increasing numbers of intelligent tutoring systems (ITSs) are embracing the integration of LLMs for digital tutoring, questions are arising as to how effective they are and if their hallucinatory behaviors diminish their perceived advantages. One critical question that is seldom asked if the availability, plurality, and relative weaknesses in the reasoning process of LLMs are contributing to the much discussed digital divide and equity and fairness in online learning. In this paper, we present an experiment with database design theory assignments and demonstrate that while their capacity to reason logically is improving, LLMs are still prone to serious errors. We demonstrate that in online learning and in the absence of a human instructor, LLMs could introduce inequity in the form of “wrongful” tutoring that could be devastatingly harmful for learners, which we call ignorant bias, in increasingly popular digital learning. We also show that significant challenges remain for STEM subjects, especially for subjects for which sound and free online tutoring systems exist. Based on the set of use cases, we formulate a possible direction for an effective ITS for online database learning classes of the future.

Jamil, Hasan M. (ORCID:0000000231243780)↗
NASA NTRS1972

Analytical design of a parasitic-loading digital speed controller for a 400-hertz turbine driven alternator

A design for a solid-state parasitic speed controller using digital logic was analyzed. Parasitic speed controllers are used in space power electrical generating systems to control the speed of turbine-driven alternators within specified limits. The analysis included the performance characteristics of the speed controller and the generation of timing functions. The speed controller using digital logic applies step loads to the alternator. The step loads conduct for a full half wave starting at either zero or 180 electrical degrees.

Ingle, B. D.↗
NASA NTRS1973

Omni-axis secondary injection thrust vector control system

The concept, development, design study and preliminary analysis and layout of the required digital logic scheme to be used for injection valve control are presented. An application and optimization study of an Omni-Axis Secondary Injection Control System applicable to the proposed Space Shuttle Pressure Fed Engine is reported. Technical definition and analysis control procedures and test routines, as well as a supporting set of drawing sketches and reference manual, are enclosed.

Kirkley, D. J.↗