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Results for “Field programmable gate array”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Design and Analysis of Digital Communication Within an SoC-Based Control System for Trapped-Ion Quantum Computing
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Control System of Multi-Port Autonomous Reconfigurable Solar Power Plant (MARS) & HIL Platforms for Design
Multi-port autonomous reconfigurable solar power plant (MARS) provides an attractive alternative to connect photovoltaic (PV) and energy storage systems (ESSs) to high-voltage direct current (HVdc) links and high-voltage alternating current (ac) grids. In this paper, a unique hierarchical control system of MARS is proposed and evaluated. To evaluate the control system and associated algorithms in early-stage research of complex architectures like MARS, it is important to develop unique suitable hardware-in-the-loop (HIL) platforms. In this paper, the HIL platforms for MARS to evaluate the performance of the hierarchical control system and the control algorithms implemented are presented. Further, they help with the design process of control systems. The real-time simulation models and algorithms that are utilized for MARS in the HIL platforms are also discussed in the paper. The HIL experiments of the control system of MARS showcase the capability to provide continuity of operation under faults and frequency support to the power grid during loss of generation. They also showcase the stability of the proposed hierarchical control system of MARS.
High-count rate effects in event processing for XRISM/ Resolve X-ray microcalorimeter: I. Ground test
The spectroscopic performance of an X-ray microcalorimeter is compromised at high count rates. We utilize the Resolve X-ray microcalorimeter onboard the XRISM satellite to examine the effects observed during high-count rate measurements and propose modeling approaches to mitigate them. We specifically address the following instrumental effects that impact performance: CPU limit, pile-up, and untriggered electrical cross-talk. Experimental data at high count rates were acquired during ground testing using the flight model instrument and a calibration X-ray source. In the experiment, data processing not limited by the performance of the onboard CPU was run in parallel, which cannot be done in orbit. This makes it possible to access the data degradation caused by limited CPU performance. We use these data to develop models that allow for a more accurate estimation of the aforementioned effects. To illustrate the application of these models in observation planning, we present a simulated observation of GX 13+1. Understanding and addressing these issues is crucial to enhancing the reliability and precision of X-ray spectroscopy in situations characterized by elevated count rates.
Passband Signal Detection at the Edge
Algorithms for radio frequency (RF) spectrum awareness need to be compatible with edge hardware to be practical for many applications. We developed a signal detection and classification model for the ZCU111 RF System-on-a-Chip (RFSoC) that operates on the fast Fourier transform of passband RF data. The system can detect and classify multiple signals of interest and display the predictions in real-time. The model consists of a modified ConvNeXt backbone and YOLOv3 head to operate on the Deep Learning Processing Unit on the RFSoC. We gathered datasets for training and testing by using a software defined radio to transmit example signals of Wi-Fi 802.11 b/g, Wi-Fi 802.11 n, FM Radio, LTE and LTE-M. By leveraging multiple inputs on the RFSoC frontend, the datasets span up to 4 GHz of bandwidth. The models showed high performance in classification accuracy, center frequency error, bandwidth error, and detection accuracy for both single and multi-signal datasets.
Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics
Graph neural networks have been shown to achieve excellent performance for several crucial tasks in particle physics, such as charged particle tracking, jet tagging, and clustering. An important domain for the application of these networks is the FGPA-based first layer of real-time data filtering at the CERN Large Hadron Collider, which has strict latency and resource constraints. We discuss how to design distance-weighted graph networks that can be executed with a latency of less than one μs on an FPGA. To do so, we consider a representative task associated to particle reconstruction and identification in a next-generation calorimeter operating at a particle collider. We use a graph network architecture developed for such purposes, and apply additional simplifications to match the computing constraints of Level-1 trigger systems, including weight quantization. Using the hls4ml library, we convert the compressed models into firmware to be implemented on an FPGA. Performance of the synthesized models is presented both in terms of inference accuracy and resource usage.
Experimental Validation of a Modular All-Electric Power Take-Off Topology for Wave Energy Converter Enabling Marine Renewable Energy Interconnection
Power electronic converters are an enabling technology for the emerging marine energy applications, such as using ocean waves to produce electricity. This paper outlines the power take-off system and its key components used in a wave energy converter offering modularity and scalability to generate power efficiently. The proposed power take-off system was implemented based on a modular multilevel converter and could be deployed to convert any alternating current electrical energy to a different alternating current for interconnection to grid or non-grid applications. Examples of widespread deployment are supplying electricity to coastal communities or producing clean drinking water. The analysis using both the simulation tests and laboratory experiments verified the design objectives and basic functionality of the developed power take-off system. An acceptable response using a field programmable gate array-based controlled laboratory testbench was achieved, complying with guidelines specified in the prevalent industry standards. Seamless operation during steady-state and transients for the studied wave energy converter was achieved as supported by the obtained results. The key findings of this work were experimentally examined under different load conditions, direct current bus voltage fluctuations, and generator speed–torque regulation. The ability of the power take-off system to generate high-power quality of the waveforms, e.g., against adhering to the IEEE 519-2022 standard for total harmonic distortion limits, is also confirmed.
Real-time non-invasive eyetracking and gaze-point determination for human-computer and biomedicine
We propose a new non-invasive visual eyetracking system that is capable of operating at speeds as high as 6-12 KHz.
Design and demonstration of an advanced on-board processor for the second-generation precipitation radar
The Next-Generation Precipitation Radar (PR-2) prototyped by NASA/JPL will depend heavily on high-performance digital processing to collect meaningful echo data.
An advanced on-board processor and adaptive scanning controller for the next-generation precipitation radar
The Next-Generation Precipitation Radar prototyped by NASA/JPL will depend heavily on high performance digital processing to collect meaningful rain echo data.
Design and verification of the second-generation precipitation radar processor/controller
In this paper, we will cover our recent progress in developing and testing one particular aspect of the PR-2 design - the electronic on-board processor/controller module.
Real-time non-invasive eyetracking and gaze-point determination for human-computer interaction and biomedicine
Eyetracking is one of the latest technologies that has shown potential in several areas including human-computer interaction for people with and without disabilities, and for noninvasive monitoring, detection, and even diagnosis of physiological and neurological problems in individuals.
Fault tolerant state machines
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VirtexII 3000 FPGA dynamic burn-in test for military and aerospace applications
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The wide swath ocean altimeter: radar interferometry for global ocean mapping with centimetric accuracy
We have developed an instrument concept that combines a conventional nadir altimeter with a radar interferometer to meet the above requirements. In this paper, we describe the overall mission concept and the interferometric radar design. We also describe several new technology developments that facilitate the inclusion of this instrument on a small, inexpensive spacecraft bus. Those include ultra-light, deployable reflectarray antennas for the radar interferometer; a novel five frequency feed horn for the radiometer and altimeter; a lightweight, low power integrated three frequency radiometer; and a field programmable gate array-based onboard data processor. Finally, we discuss recent algorithm developments for the onboard date processing, and present the expected instatements performance improvements over previously reported results.
Catastrophic Fault Recovery with Self-Reconfigurable Chips
Mission critical systems typically employ multi-string redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use of 'Self-Reconfigurable Chips' as a last resort effort to 'repair' a faulty critical component.
An Interleaver Implementation for the Serially Concatenated Pulse-Position Modulation Decoder
We describe novel interleaver and deinterleaver architectures that support bandwidth efficient memory access for decoders of turbo-like codes that are used in conjunction with high order modulations. The presentation focuses on a decoder for serially concatenated pulse-position modulation (SCPPM), which is a forward-error-correction code designed by NASA to support laser communications from Mars at more than 50 megabits-per-second (Mbps). For 64-ary PPM, the new architectures effectively triple the fan-in of the interleaver and fan-out of the deinterleaver, enabling parallelization that doubles the overall throughput. The techniques described here can be readily modified for other PPM orders.
Acceleration of Stereo Correlation in Verilog
To speed up vision processing in low speed, low power devices, embedding FPGA hardware is becoming an effective way to add processing capability. FPGAs offer the ability to flexibly add parallel and/or deeply pipelined computation to embedded processors without adding significantly to the mass and power requirements of an embedded system. This paper will discuss the JPL stereo vision system, and describe how a portion of that system was accelerated by using custom FPGA hardware to process the computationally intensive portions of JPL stereo. The architecture described takes full advantage of the ability of an FPGA to use many small computation elements in parallel. This resulted in a 16 times speedup in real hardware over using a simple linear processor to compute image correlation and disparity.