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At least 541 records · Page 30

Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the class of applications with moderate input-output data rates but large intermediate multi-thread data streams has been addressed and mitigated. This opens a new class of satellite image processing applications for bottleneck problems solution using RC technologies. The issue of a science algorithm level of abstraction necessary for RC hardware implementation is also described. Selected Matlab functions already implemented in hardware were investigated for their direct applicability to the GOES-8 application with the intent to create a library of Matlab and IDL RC functions for ongoing work. A complete class of spacecraft image processing applications using embedded re-configurable computing technology to meet real-time requirements, including performance results and comparison with the existing system, is described in this paper.

Kizhner, Semion↗

Marsviewer

Marsviewer is a multi-platform application designed to aid in quality control, browsing, and analysis of original science product images (Experiment Data Records, or EDRs) and derived image data products (Reduced Data Records, or RDRs) returned by the Mars Explorer Rover (MER) mission. Marsviewer offers an abstraction of the products organization via a file finder. For example, the application understands the file structure and filename conventions of the MER Operational Storage Server, helping the user to navigate this complex file system to find desired images. Marsviewer also works with a flat file system, remote-operations file systems, image-archive file systems, and others. All EDRs found for a given solar day (Sol) are displayed in a list, optionally with thumbnail images. Once the user selects an image from the list, a tabbed pane conveniently displays the original source image and all associated RDRs. Marsviewer provides the option of overlaying derived images upon the source image, resulting in an easier-to-interpret color representation of the data. Display manipulations such as zoom, data range adjustment, contrast enhancement, and contour control are available. Image metadata (labels) from the current image can be displayed and searched. The architecture of the program is extensible: new types of RDRs can be installed and new file finders can be added to adapt the program to different file structures and different filename conventions. This keeps the application flexible and provides an opportunity for reuse with future rover missions.

Toole, Nicholas↗

Rotorcraft airframe structural optimization for combined vibration and fatigue constraints

This paper addresses the application of a formal optimization technique in rotorcraft airframe structural design studies to reduce the structural weight, to lower airframe vibrations, and to enhance fatigue life of the structure. Vibration and fatigue considerations in airframe design are described. An optimization methodology based on the use of a nonlinear programming technique to size airframe structural members subjected to constraints on weight, vibration response and fatigue stresses under dynamic loads, are described. The paper focuses on the development of necessary computational tools for airframe structural optimization and describes the sensitivity analysis procedure for these types of design constraints. Further, the paper describes the optimization procedure as implemented in a computer code called DYNOPT which is a unique operational combination of several newly developed Fortran codes as well as modification of existing codes consisting of the direct matrix abstraction modules of the MSC/NASTRAN Program and CONMIN optimizer. The application of the optimization procedure is demonstrated using an elastic-line model of the Bell AH-1G helicopter airframe structure and computational results are discussed.

Sareen, Ashish K.↗

(abstract) A High Throughput 3-D Inner Product Processor

A particularily challenging image processing application is the real time scene acquisition and object discrimination. It requires spatio-temporal recognition of point and resolved objects at high speeds with parallel processing algorithms. Neural network paradigms provide fine grain parallism and, when implemented in hardware, offer orders of magnitude speed up. However, neural networks implemented on a VLSI chip are planer architectures capable of efficient processing of linear vector signals rather than 2-D images. Therefore, for processing of images, a 3-D stack of neural-net ICs receiving planar inputs and consuming minimal power are required. Details of the circuits with chip architectures will be described with need to develop ultralow-power electronics. Further, use of the architecture in a system for high-speed processing will be illustrated.

imaging parallel processing algorithms linear vect↗