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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Final Technical Report: Innovative Magnetron Power Sources for Superconducting RF (SRF) Accelerators

In this project, MUONS is designing and building custom magnetrons at Richardson Electronics (RELL) to test the predictions of the models and make improvements to the designs to match the needs of NP SRF accelerators and their life-cycle costs. To increase lifetime, the filament temperature is controlled by a feedback circuit that includes a model of back streaming of electrons. The gain of the magnetron is optimized by the design of an input port. A permanent magnet design with trim coil for amplitude adjustment reduces energy consumption. Moving the construction of the magnetron from prototype to manufacturing includes the utilization of RELL processes and designs. To the extent that outgassing of materials influences the lifetime of the magnetron, methods for minimizing outgassing was explored. Further experimentation of the potential of sub-critical voltage operation continues to be explored. The commercialization goal of the project will be naturally achieved as RELL already has world-wide marketing, sales, and support to exploit the assembly-line capabilities generated by this project to enable magnetron technologies for NP accelerators.

43 PARTICLE ACCELERATORS↗
DOE OSTI2021

Accelerating Transformer-based Deep Learning Models on FPGAs using Column Balanced Block Pruning

Although Transformer-based language representations achieve state-of-the-art accuracy on various natural language processing (NLP) tasks, the large model size has been challenging the resource constrained computing platforms. Weight pruning, as a popular and effective technique in reducing the number of weight parameters and accelerating the Transformer, has been investigated on GPUs. However, the Transformer acceleration using weight pruning on field-programmable gate array (FPGAs) remains unexplored. This paper investigates the column balanced block-wise pruning on Transformer and designs an FPGA acceleration engine to customize the balanced blockwise matrix multiplication. We implement the Transformer model with proper hardware scheduling, and the experiments show that the Transformer inference on FPGA achieves 10.35 ms latency with the batch size of 32, which is 10.96 × speed up comparing to CPU platform and 2.08 × speed up comparing to GPU platform.

Peng, Hongwu↗
DOE OSTI2021

Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operationson Spatial Accelerators

To meet the extreme compute demands for deep learning across commercial and scientific applications, dataflow accelerators are becoming increasingly popular. While these“domain-specific” accelerators are not fully programmable like CPUs and GPUs, they retain varying levels of flexibility with respect to data orchestration, i.e., dataflow and tiling optimizations to enhance efficiency. There are several challenges when designing new algorithms and mapping approaches to execute the algorithms for a target problem on new hardware. Previous works have addressed these challenges individually. To address this challenge as a whole, in this work, we present an HW-SW co-design ecosystem for spatial accelerators called Union within the popular MLIR compiler infrastructure. Our framework allows exploring different algorithms and their mappings on several accelerator cost models. Union also includes a plug-and-play library of accelerator cost models and mappers which can easily be extended. The algorithms and accelerator cost models are connected via a novel mapping abstraction that captures the map space of spatial accelerators which can be systematically pruned based on constraints from the hardware, workload, and mapper. We demonstrate the value of Union for the community with several case studies which examine offloading different tensor operations (CONV/GEMM/Tensor Contraction) on diverse accelerator architectures using different mapping schemes.

Jeong, Geonhwa↗
DOE OSTI2020

Design and Analysis of a Double Wall, Water Cooled Window for Accelerator Based Mo-99 Production

The electron accelerator based Mo-99 production technique requires the use of Rhodotrons to generate 38 MeV, 6.32 mA pulsed electron beams. The introduction of the pulsed beam structure has introduced fatigue concerns in the vacuum-helium windows that did not exist previously for electron beam production via linear accelerators. Previous analysis has shown that temperature fluctuations of approximately 100°C above and below the steady state operating temperature of ~500°C will occur within the windows. A water cooled window will eliminate this concern by reducing the primary mechanical stress due to the 300-psig helium pressure load as well as the secondary thermally induced stress. Although a water cooled window was considered years ago, the complexities of adding an additional water line was unattractive until now. A double wall, water cooled window has been designed and analyzed for this reason. The water cooled window design is shown to decrease the helium-side window temperature to as low as 125°C, while the vacuum-side window is maintained at 161°C at a water flow rate of 3.2 GPM. These low steady state temperatures reduce the thermal stress of the helium-side window significantly. Also, the primary mechanical stress has been reduced by roughly 50% due to the reduced pressure gradient across the helium-side window (150-psig water and 300-psig helium). Considering a Mo-99 production loss of roughly 1%, the water cooled window is a drastic improvement over the previous helium cooled designs and should be greatly considered for future upgrades and redesign.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

Improved melt model for power flow

Accelerators that drive z-pinch experiments transport current densities in excess of 1 MA/cm 2 in order to melt or ionize the target and implode it on axis. These high current densities stress the transmission lines upstream from the target, where rapid electrode heating causes plasma formation, melt, and possibly vaporization. These plasmas negatively impact accelerator efficiency by diverting some portion of the current away from the target, referred to as “current loss”. Simulations that are able to reproduce this behavior may be applied to improving the efficiency of existing accelerators and to designing systems operating at ever higher current densities. The relativistic particle-in-cell code CHICAGO ® is the primary code for modeling power flow on Sandia National Laboratories’ Z accelerator. We report here on new algorithms that incorporate vaporization and melt into the standard power-flow simulation framework. Taking a hybrid approach, the CHICAGO® kinetic/multi-fluid treatment has been expanded to include vaporization while the quasi-neutral equation-of-motion has been updated for melt at high current-densities. For vaporization, a new one-dimensional substrate model provides a more accurate calculation of electrode thermal, mass, and magnetic field diffusion as well as a means of emitting absorbed contaminants and vaporized metal ions. A quasi-fluid model has been implemented expressly to mimic the motion of imploding liners for accurate inductance histories. For melt, a multi-ion Hall-MHD option has been implemented and benchmarked against Alegra MHD. This new model is described with sufficient detail to reproduce these algorithms in any hybrid kinetic code. Physics results from the new code are also presented. A CHICAGO ® Hall-MHD simulation of a radial transmission line demonstrates that Hall physics, not included in Alegra, has no significant impact on the diffusion of electrode material. When surface contaminant desorption is mocked in as a hydrogen surface plasma, both the surface and bulk-material plasmas largely compress under the influence of the j × B force. Similar results are seen in Alegra, which also shows magnetic and material diffusion scaling with peak current. Test vaporization simulations using MagLIF and a power-flow experimental geometry show Fe + ions diffuse only a few hundred µm from the electrodes, so present models of Z power flow remain valid.

43 PARTICLE ACCELERATORS↗
DOE OSTI2022

European Strategy for Particle Physics -- Accelerator R&D Roadmap

The 2020 update of the European Strategy for Particle Physics emphasised the importance of an intensified and well-coordinated programme of accelerator R&D, supporting the design and delivery of future particle accelerators in a timely, affordable and sustainable way. This report sets out a roadmap for European accelerator R&D for the next five to ten years, covering five topical areas identified in the Strategy update. The R&D objectives include: improvement of the performance and cost-performance of magnet and radio-frequency acceleration systems; investigations of the potential of laser / plasma acceleration and energy-recovery linac techniques; and development of new concepts for muon beams and muon colliders. The goal of the roadmap is to document the collective view of the field on the next steps for the R&D programme, and to provide the evidence base to support subsequent decisions on prioritisation, resourcing and implementation.

43 PARTICLE ACCELERATORS↗
DOE OSTI2021

Design of double- and multi-bend achromat lattices with large dynamic aperture and approximate invariants

A numerical method to design nonlinear double- and multi-bend achromat (DBA and MBA) lattices with approximate invariants of motion is investigated. The search for such nonlinear lattices is motivated by Fermilab’s Integrable Optics Test Accelerator (IOTA), whose design is based on an integrable Hamiltonian system with two invariants of motion. While it may not be possible to design an achromatic lattice for a dedicated synchrotron light source storage ring with one or more exact invariants of motion, it is possible to tune the sextupoles and octupoles in existing DBA and MBA lattices to produce approximate invariants. In our procedure, the lattice is tuned while minimizing the turn-by-turn fluctuations of the Courant-Snyder actions J x and J y at several distinct amplitudes, while simultaneously minimizing diffusion of the on-energy betatron tunes. The resulting lattices share some important features with integrable ones, such as a large dynamic aperture, trajectories confined to invariant tori, robustness to resonances and errors, and a large amplitude-dependent tune-spread. Compared to the nominal NSLS-II lattice, the single- and multi-bunch instability thresholds are increased and the bunch-by-bunch feedback gain can be reduced.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

MLIR loop optimizations for High-Level Synthesis: a case study

High-Level Synthesis (HLS) tools simplify the design of hardware accelerators by automatically generating Verilog/VHDL code starting from a general purpose software programming language. They include a wide range of optimization techniques in the process, most of them performed on a low-level intermediate representation (IR) of the code. Introducing optimizations on a higher level of abstraction could significantly contribute to the automated design process results; for example, polyhedral techniques for the manipulation of loops could have a significant impact on the generated accelerators when applied on a specialized IR. We use loop pipelining as a case study to explore the introduction of compiler-based transformations on top of an existing HLS process. We leverage the Multi-Level Intermediate Representation (MLIR) framework and an external scheduler to implement the required transformations, and couple them with existing HLS tools to evaluate the improvements that loop pipelining brings to the performance of generated accelerators. The proposed approach can be integrated with other high-level transformations on the MLIR representation, combining different techniques to obtain pre-optimized inputs for HLS that do not have to rely on a specific backend tool.

Curzel, Serena↗
DOE OSTI2022

Chapter 10: Advances in Protein Engineering and its Application in Synthetic Biology

Protein engineering has been used successfully in fields ranging from medicine to food science to biofuels. Applications of protein engineering include developing antiviral peptides or other protein therapeutics, antibody engineering, designing protein-based logic circuits, engineering enzymes to be more specific or to function under industrially relevant conditions such as at higher temperatures or high/low pH, modifying cell signaling or regulatory functions, and so on. Advances in recombinant DNA, "omics," and CRISPR-Cas (clustered regularly interspaced short palindromic repeats and its associated proteins) technologies, combined with high-throughput screening facilities, will lead to improved methods for protein engineering, enabling easy modification of more proteins/enzymes for new specific applications. New methods for rational design, directed evolution, and computer-aided protein design will further accelerate the speed of protein evolution and expand the scope for protein engineering. In this chapter we discuss general protein engineering strategies and advances in engineering proteins with desired functions, focusing on the "design" and "build" part of the design-build-test-learn cycle.

BIOMASS FUELS↗
DOE OSTI2021

High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers

The increased need for efficient ways to implement domain-specific accelerators is driving design methodologies towards the use of abstractions higher than the Register Transfer Level (RTL). In this scenario, High Level Synthesis (HLS) plays a significant role by enabling the automatic generation of custom hardware accelerators starting from high level descriptions (e.g., C code). Conventional HLS tools exploit parallelism mostly at the Instruction Level (ILP). They statically schedule the input specifications, and build centralized Finite State Machine (FSM) controllers. However, aggressive exploitation of ILP in many applications has diminishing returns and, usually, centralized approaches do not efficiently exploit coarser parallelism because FSMs are inherently serial. In this paper we present a HLS framework able to synthesize applications that, beside ILP, also expose Task Level Parallelism (TLP). An application can expose TLP through annotations that identify the parallel functions (i.e., tasks). To generate accelerators that efficiently execute concur- rent tasks, we need to solve several issues: devise a mechanism to support concurrent execution flows, exploit memory parallelism, and manage synchronization. To support concurrent execution flows, we introduce a novel adaptive controller. The adaptive controller is composed of a set of interacting control elements that independently manage the execution of a single operation or function call. These control elements check dependencies and resource constraints at runtime, enabling as soon as possible execution. To support parallel access to shared memories and synchronization, we introduce a novel Hierarchical Memory Interface (HMI). With respect to previous solutions, the proposed interface supports multi-ported memories and atomic memory operations, which commonly occur in parallel programming. Our framework can generate the hardware implementation of C functions by employing two different approaches, depending on its characteristics. If a function exposes TLP, then the framework generates hardware implementations based on the adaptive controller. Otherwise, the framework implements the function by exploiting a more conventional FSM approach, which is optimized for ILP exploitation. We evaluate our framework on a set of parallel applications, and show substantial performance improvements (average speedup of 4.7) with limited area over- heads (average area increase of 5.48 times).

Castellana, Vito G.↗
DOE OSTI2021

High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers

The increased need for efficient ways to implement domain-specific accelerators is driving design methodologies towards the use of abstractions higher than the Register Transfer Level (RTL). In this scenario, High Level Synthesis (HLS) plays a significant role by enabling the automatic generation of custom hardware accelerators starting from high level descriptions (e.g., C code). Conventional HLS tools exploit parallelism mostly at the Instruction Level (ILP). They statically schedule the input specifications, and build centralized Finite State Machine (FSM) controllers. However, aggressive exploitation of ILP in many applications has diminishing returns and, usually, centralized approaches do not efficiently exploit coarser parallelism because FSMs are inherently serial. In this paper we present a HLS framework able to synthesize applications that, beside ILP, also expose Task Level Parallelism (TLP). An application can expose TLP through annotations that identify the parallel functions (i.e., tasks). To generate accelerators that efficiently execute concur- rent tasks, we need to solve several issues: devise a mechanism to support concurrent execution flows, exploit memory parallelism, and manage synchronization. To support concurrent execution flows, we introduce a novel adaptive controller. The adaptive controller is composed of a set of interacting control elements that independently manage the execution of a single operation or function call. These control elements check dependencies and resource constraints at runtime, enabling as soon as possible execution. To support parallel access to shared memories and synchronization, we introduce a novel Hierarchical Memory Interface (HMI). With respect to previous solutions, the proposed interface supports multi-ported memories and atomic memory operations, which commonly occur in parallel programming. Our framework can generate the hardware implementation of C functions by employing two different approaches, depending on its characteristics. If a function exposes TLP, then the framework generates hardware implementations based on the adaptive controller. Otherwise, the framework implements the function by exploiting a more conventional FSM approach, which is optimized for ILP exploitation. We evaluate our framework on a set of parallel applications, and show substantial performance improvements (average speedup of 4.7) with limited area over- heads (average area increase of 5.48 times).

Castellana, Vito G.↗
DOE OSTI2020

Sensitivity Studies, Gap Analysis, and Benchmark Experiment Optimization for Reactor Applications

In regards to nuclear data, some reactor applications may lack validation experiments, which reduces confidence in predicted results. This is especially true for emerging advanced reactor, micro reactor, and Accelerator Driven System (ADS) designs. This work presents an approach to design new criticality experiments that have similar k eff cross section sensitivities to an application of interest. This process involves simulations to generate cross-section sensitivities to a parameter of interest (such as k eff ), a gap analysis to determine which existing benchmarks are most similar to the application, and an experiment optimization. This work focuses on cross-section sensitives and gap analysis for three examples relevant to the reactor physics community including a Travelling Wave Reactor (TWR) type-design, Kilopower (a space reactor design), and a lead-bismuth eutectic cooled accelerator-driven system (ADS) to transmute minor actinides.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2025

NOVEL METHODS FOR IN SITU HIGH DENSITY SURFACE CLEANING SCRUBBING OF ULTRAHIGH VAC LONG NARROW TUBES TO REDUCE SECONDARY ELECTRON YIELD AND OUT GASSING

This project developed new methods for cleaning the inside surfaces of very long, narrow vacuum tubes used in particle accelerators. Traditional cleaning approaches are expensive, slow, or difficult to implement in accelerator tunnels. We designed and tested a portable plasma discharge cleaning system that uses lower-cost microwave and magnetron technologies to reduce outgassing and secondary electron emission from stainless steel and copper surfaces. The system, called the Plasma Discharge Test System (PDTS), allows accelerator components to be scrubbed more efficiently, which can improve performance and reduce maintenance costs for research and industrial applications.

POOLE, JOE HENRY [PRESIDENT]↗
DOE OSTI2025

Computational Design of Cost-Effective High-Entropy Thermal/Environmental Barrier Coatings

Developing cost-effective thermal/environmental barrier coatings (TEBC) requires balance among various properties including low thermal conductivity, matching coefficient of thermal expansion (CTE), high thermal stability, high fracture toughness, and high recession resistance while being affordable. Low oxygen diffusivity is desirable as it can slow down oxygen transport to reach the underlying bond coating and hence delay oxidation of the bond coating. This project aims to design low-cost high-performance TEBC based on high entropy rare earth disilicates to protect SiC-based ceramic matrix composites from chemical and thermal attack for better performance of components in the hot section of gas turbine engines. To accelerate the TEBC design, we utilize first-principles density functional theory to predict key properties including phase stability, CTE, lattice thermal conductivity, temperature-dependent elastic constants, and oxygen diffusivity. Alloying elements including Yb, Y, Er, Eu, Gd, Lu, La, and Ce are considered, and modeling prediction are compared with available experimental results.

coefficient of thermal expansion↗
DOE OSTI2022

A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining

Transformers are considered one of the most important deep learning models since 2018, in part because it establishes state-of-the-art (SOTA) records and could potentially replace existing Deep Neural Networks (DNNs). Despite the remarkable triumphs, the prolonged turnaround time of Transformer models is a widely recognized roadblock. The variety of sequence lengths imposes additional computing overhead where inputs need to be zero-padded to the maximum sentence length in the batch to accommodate the parallel computing platforms. This paper targets the field-programmable gate array (FPGA) and proposes a coherent sequence length adaptive algorithm–hardware co-design for Transformer acceleration. Particularly, we develop a hardware-friendly sparse attention operator and a length-aware hardware resource scheduling algorithm. The proposed sparse attention operator brings the complexity of attention-based models down to linear complexity and alleviates the off-chip memory traffic. The proposed length-aware resource hardware scheduling algorithm dynamically allocates the hardware resources to fill up the pipeline slots and eliminates bubbles for NLP tasks. Experiments show that our design has very small accuracy loss and has 80.2 × and 2.6 × speedup compared to CPU and GPU implementation, and 4 × higher energy efficiency than state-of-the-art GPU accelerator optimized via CUBLAS GEMM.

Peng, Hongwu↗