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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

The Imaging Properties of a Silicon Wafer X-Ray Telescope

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Joy, M. K.↗
NASA NTRS2004

Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

Simons, Rainee N.↗
DOE OSTI2024

Acoustics-based noninvasive wafer defect detection

Techniques are provided for detecting wafer defects. Example techniques include exciting a wafer using an acoustic signal to cause the wafer to exhibit vibrations, measuring one or more of linear frequency response metrics or nonlinear frequency responses metrics associated with the vibrations, and identifying any defects in the wafer based at least in part on one or more of the linear frequency response metrics or nonlinear frequency responses metrics. In embodiments, the wafer includes bismuth telluride (Bi 2 Te 3 ).

Pantea, Cristian↗
DOE OSTI2023

Integrated Ion-Exchange Membrane Resin Wafer Assemblies for Aromatic Organic Acid Separations Using Electrodeionization

Aromatic acids, such as p-coumaric acid, are valuable chemical intermediates that are used in the specialty chemical industries because they are precursors to phenylpropanoid compounds. The separation of p-coumaric acid from fermentation broths is a critical step in the biochemical production process and more broadly the circular carbon economy. Electrodeionization (EDI) has been applied toward separations of low-carbon chain acids, but purifying p-coumaric acid has been challenging due to fouling and irreversible binding with ion-exchange membranes and resins. Here, we report a new membrane wafer assembly (MWA) consisting of laminated ion exchange membranes to porous ionomer-binder resin wafers for EDI. The MWAs in an EDI stack showed a 7-fold increase in p-coumaric acid capture while also using 70% less specific energy consumption when benchmarked against state-of-the-art resin wafer EDI modules. The more efficient p-coumaric acid recovery was ascribed to (i) the 38% reduction in interfacial transport resistance between the membrane and resin wafer and (ii) using imidazolium anion exchange membranes and ionomer binders in the MWA. MD simulations revealed enhanced transport rates for p-coumarate in imidazolium ionomers through π–π interactions. As a result, adopting the new MWA significantly reduced the amount of ion-exchange membranes in EDI and may lead to drastic capital cost savings.

42 ENGINEERING↗
DOE OSTI2022

Generation of selective single-mode guided waves by d 36 type piezoelectric wafer

In general, mixed modes and dispersion of guided wave occur at any excitation frequency, while single modes are needed for effective nondestructive evaluation of structures. In this work, we present an approach to generate a selective single-mode guided wave in plate-like structures by exploiting the unique directionality of the d 36 type piezoelectric wafer and the symmetry of fundamental guided wave modes. Specifically, we devise a unified fundamental shear horizontal (SH 0 ) wave/fundamental antisymmetric mode (A 0 ) wave directional transducer pair by attaching the d 36 type piezoelectric wafers back to back on the opposite sides of the plate to provide selective, directional single-mode guided waves for actuation and sensing. Originally, the d 36 -type piezoelectric wafer, poled and cut from the lead magnesium niobate-lead titanate crystal, produces a mixture of the in-plane SH 0 (symmetric) mode and out-of-plane A 0 (asymmetric) and S 0 (symmetric) modes. By applying the in-phase or out-of-phase applied electrical field to the coupled d 36 -type piezoelectric wafer pair, our devised approach generates selective single modes, SH 0 or A 0 , respectively, to propagate in the structure. We describe the theoretical development of our approach and conduct both numerical simulations and laboratory experiments for validations.

42 ENGINEERING↗
DOE OSTI2023

Nature of contaminants introduced in silicon wafers during molecular beam epitaxy chamber annealing

Epitaxial monolithic III–V/Si tandem solar cells are one of the most promising technologies to be adopted by the industry after the efficiency of the current market dominating single junction silicon solar cell saturates at its fundamental limit. One of the key limitations of this technology is the degradation of silicon wafers during in situ annealing in the molecular beam epitaxy chamber. Determining the nature of contaminants in this process is key to improve the efficiency of epitaxial tandem solar cells. However, to date, the nature of contaminants from molecular beam epitaxy chambers remains unknown. In this work, we use photoluminescence imaging, lifetime spectroscopy, and deep level transient spectroscopy to measure the electronic properties of extrinsic impurities incorporated during annealing in the molecular beam epitaxy chamber. Photoluminescence images reveal that at least two impurities diffuse into silicon wafers during molecular beam epitaxy annealing. One is highly localized, while the other one is distributed uniformly across the whole wafer. Phosphorus diffusion is found to confine the localized impurity within the diffused layer but is ineffective at preventing the indiffusion of other impurities. Lifetime spectroscopy shows that metastable impurities with characteristic similar to Cr and CrB in our molecular beam epitaxy annealed silicon wafers. No evidence of Fe or FeB was observed. The emission rates and concentrations of the electrically active defects were measured with deep-level transient spectroscopy: The emission rates of detected defects do not match that of known Cr-related defects.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Specifications and pre-production of n + -in-p large-format strip sensors fabricated in 6-inch silicon wafers, ATLAS18, for the Inner Tracker of the ATLAS Detector for High-Luminosity Large Hadron Collider

Abstract The ATLAS experiment is constructing new all-silicon inner tracking system for HL-LHC. The strip detectors cover the radial extent of 40 to 100 cm. A new approach is adopted to use p-type silicon material, making the readout in n + -strips, so-called n + -in-p sensors. This allows for enhanced radiation tolerance against an order of magnitude higher particle fluence compared to the LHC. To cope with varying hit rates and occupancies as a function of radial distance, there are two barrel sensor types, the short strips (SS) for the inner 2 and the long strips (LS) for the outer 2 barrel cylinders, respectively. The barrel sensors exhibit a square, 9.8 × 9.8 cm 2 , geometry, the largest possible sensor area from a 6-inch wafer. The strips are laid out in parallel with a strip pitch of 75.5 μm and 4 or 2 rows of strip segments. The strips are AC-coupled and biased via polysilicon resistors. The endcap sensors employ a “stereo-annulus” geometry exhibiting a skewed-trapezoid shapes with circular edges. They are designed in 6 unique shapes, R0 to R5, corresponding to progressively increasing radial extents and which allows them to fit within the petal geometry and the 6-inch wafer maximally. The strips are in fan-out geometry with an in-built rotation angle, with a mean pitch of approximately 75 μm and 4 or 2 rows of strip segments. The eight sensor types are labeled as ATLAS18xx where xx stands for SS, LS, and R0 to R5. According to the mechanical and electrical specifications, CAD files for wafer processing were laid out, following the successful designs of prototype barrel and endcap sensors, together with a number of optimizations. A pre-production was carried out prior to the full production of the wafers. The quality of the sensors is reviewed and judged excellent through the test results carried out by vendor. These sensors are used for establishing acceptance procedures and to evaluate their performance in the ATLAS collaboration, and subsequently for pre-production of strip modules and stave and petal structures.

Instruments & Instrumentation↗
DOE OSTI2025

Wafer-scale waveguide sidewall roughness scattering loss characterization by image processing

Photonic integrated circuits (PICs) are vital for developing affordable, high-performance optoelectronic devices that can be manufactured at an industrial scale, driving innovation and efficiency in various applications. Optical loss of modes in thin film waveguides and devices is a critical measure of their performance. Thin film growth, lithography, masking, and etching processes are imperfect processes that introduce significant sidewall and top-surface roughness and cause dominating optical losses in waveguides and photonic structures. This roughness, as perturbations couple light from guided to far-field radiation modes, leads to scattering losses that can be estimated from theoretical models. Typically, with UV-based lithography, sidewall roughness is significantly larger than wafer-top surface roughness. Atomic force microscopy (AFM) imaging measurement gives a 3D and high-resolution roughness profile, but the measurement is inconvenient, costly, and unscalable for large-scale PICs and at wafer-scale. Here, we evaluate the sidewall roughness profile based on 2D high-resolution scanning electron microscope (SEM) imaging. We characterized the loss on two homemade nitride and oxide films on 3-inch silicon wafers with 12 waveguide devices on each and correlated the scattering loss estimated from a 2D image-based sidewall profile and theoretical Payne model. The lowest loss of guided fundamental transverse electric (TE 0 ) mode is found at 0.075 dB/cm at 633 nm across 24 devices, a record at visible wavelength. Our work shows 100% success (edge continuity span exceeding 95% of image width/height) in edge detection in image processing of all images to estimate autocorrelation function and optical mode loss. These demonstrations offer valuable insights into waveguide sidewall roughness and a comparison of experimental and 2D SEM image processing based loss estimations with applications in loss characterization at wafer-scale PICs.

Khurana, Mohit (ORCID:0000000207898672)↗
DOE OSTI2022

Excess carrier concentration in silicon devices and wafers: How bulk properties are expected to accelerate light and elevated temperature degradation

Light and elevated temperature induced degradation (LeTID) is accelerated nearly linearly by the presence of excess carriers. It is therefore important to understand how excess carrier concentration (Δn) changes as a function of exposure conditions, materials properties, and sample structure. We simulate Δn as a function of wafer thickness and bulk minority carrier lifetime (τ) in solar cells and wafers using SCAPS and Quokka3. We also derive closed-form analytic expressions. For wafers, there is a near-linear relationship between Δn and τ or thickness, whereas for solar cells, Δn in the bulk may become limited by rear surface recombination. Thus, LeTID may progress more quickly in wafers than in cells, with a stronger dependence on τ. When comparing experiments, observed degradation rates must be corrected between samples or conditions to account for differences in Δn. This study demonstrates three tools to estimate the magnitude of such corrections, which can aid in the quantitative interpretation of LeTID data and performance predictions. Finally, while each tool yields similar results, there are advantages to each approach that must be weighed in terms of simplicity of inputs versus sophistication of treatment. Incomplete specification of back contact characteristics in commercial products is identified as an important contributor to uncertainty in expected LeTID rates.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Multiplication of freestanding III-V semiconductor membranes from a single wafer by alternating growth with amorphous graphene interlayer

Freestanding single-crystalline III-V compound semiconductors are important building blocks for functional devices due to their high electron mobilities, a wide range of bandgaps, and excellent optoelectronic properties. Despite efforts to produce such membranes by detaching epitaxial layers from donor wafers, current methods suffer from either slow processes or poor material quality. Here, we demonstrate a technique to grow and harvest multiple epitaxial membranes with extremely high throughput at the wafer scale. For this, a process to directly grow amorphous graphene on III-V substrates in metal-organic chemical vapor deposition reactors is developed, which enables an advanced remote epitaxy scheme comprised of multiple alternating layers of amorphous graphene and III-V epitaxial layers that can be formed by a single epitaxy run. Each epilayer in the multi-stack structure is then harvested by layer-by-layer peeling, producing multiple freestanding membranes with unprecedented throughput from a single wafer. Because amorphous graphene provides a weak van der Waals interface that allows peeling at the interface without damaging the epilayer or the substrate, wafers can be reused for subsequent membrane production. Therefore, this work represents a meaningful step toward high-throughput and low-cost production of single-crystal membranes that can be heterointegrated.

Han, Ne Myo↗
NASA NTRS1978

Multi-wire slurry wafering demonstrations

Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

Chen, C. P.↗
NASA NTRS1979

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

Jones, G. T.↗
NASA NTRS1981

An experimental investigation of silicon wafer surface roughness and its effect on the pull-strength of plated metals

Plated silicon wafers with surface roughness ranging from 0.4 to 130 microinches, subjected to tensile pull-strength tests, were analyzed. Results show that the measured pull-strength of plated metals decrease with increasing silicon surface roughness, effecting a weakening of the cohesive strength of the wafer, possibly caused by microcracks or 'etch pits' in the silicon surface. The mean value of pull-strength for all wafers plated with the Ni-Cu-Cu sequence exceeded the required 450 g/0.02 sq cm, and at Ra = 0.4 microinches, the mean pull-strength for the Ni-Cu-Cu and Ni-Cu wafers were 2290 and 850 g/0.02 sq cm, respectively. The development of standardized methods for measuring contact pull-strength is suggested. These results may have some bearing on solar cell arrays problems.

Spiers, G. D.↗
NASA NTRS1981

Forming electrical interconnections through semiconductor wafers

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Anthony, T. R.↗
NASA NTRS1981

Scriber for silicon wafers

A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

Yamakawa, K. A.↗
NASA NTRS1985

Reciprocating Saw for Silicon Wafers

Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

Morrison, A. D.↗
NASA NTRS1989

Spinner For Etching Of Semiconductor Wafers

Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

Lombardi, Frank↗
NASA NTRS1999

Low Loss, Finite Width Ground Plane, Thin Film Microstrip Lines on Si Wafers

Si RFICs on standard, 2 Omega-cm. Si wafers require novel transmission lines to reduce the loss caused by the resistive substrate. One such transmission line is commonly called Thin Film Microstrip (TFMS), which is created by depositing a metallic ground plane, thin insulating layers, and the microstrip lines on the Si wafer. Thus, the electric fields are isolated from the Si wafer. In this paper, it is shown through experimental results that the ground plane of TFMS may be finite width and comparable to the strip width in size while still achieving low loss on 2 Omega-cm Si. Measured effective permittivity shows that the field interaction with the Si wafer is small.

Ponchak, George E.↗