Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “transistors”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Thermally Stable Ruthenium Contact for Robust p‑Type Tellurium Transistors

Tellurium (Te) is attractive for p-channel transistors due to its high hole mobility. Despite having a low thermal budget suitable for back-end-of-line (BEOL) monolithic integration, the practical realization of Te transistors is hindered by its thermal stability. In this work, we investigate thermal stability for Te thin films grown via scalable thermal evaporation. Our findings identify ruthenium as a more thermally stable contact for p-type Te transistors, capable of withstanding temperatures up to 250 °C. Ruthenium exhibits significantly lower diffusivity in Te compared to other contact metals commonly used such as nickel and palladium. Using the transfer-length method, we measured a contact resistance of 1.25 kΩ·μm at the ruthenium-tellurium interface. Additionally, the incorporation of high-κ ZrO2 encapsulation not only suppresses the sublimation of the Te channel at elevated temperatures but also serves as the gate dielectric in top-gate devices operating at 1 V, achieving an on/off current ratio of 105.

Rahman, I K M Reaz↗
DOE OSTI2026

GaN Core-shell Nanofin Vertical Transistor (CoNVerT): A New Direction for Power Electronics (Final Scientific/Technical Report)

A novel power transistor architecture, the GaN c ore-shell n anofin ver tical transistor (CoNVerT) to address fundamental challenges in realizing the ultimate limit of GaN power transistor performance was explored experimentally. This technology promises ultra-high-efficiency high voltage/high power applications (e.g. DC/DC converters, motor control, fast charging, actuation), as well as to operate in harsh environments. The device exploits a vertical superjunction structure based on an experimentally-validated core-shell nanofin growth process in which lateral p-n heterojunctions are formed in a single growth step, while still maintaining vertical current flow for compact die size and low cost. The concept leverages the best properties of GaN for mid-range voltage applications: high mobility, high breakdown voltage, and native heterojunction enhancement-mode operation. Due to the crystallographic nature of the nanofin growth by molecular beam epitaxy, the sidewall heterojunctions occur on non-polar planes, resulting in ultra-smooth interfaces for high mobility, no sidewall etch damage and related surface/interface states, and elimination of piezoelectric effects that can limit reliability in conventional structures. This also facilitates superjunction formation for maximum device performance, and the selective-area growth of the nanofin results in dislocation-free growth, even on low-cost Si (111) substrate. In this program, core-shell nanofins were grown by molecular beam epitaxy, test structures to evaluate the doping, resistivity, and other electrical properties were fabricated, and the material and test structures were characterized in detail. The work identified clear potential (e.g., the doping was well controlled as required for superjunction concepts), but also additional areas that require additional effort to resolve (some unexpected crystal defects were encountered that require additional engineering to overcome). Simulation studies of the proposed concept validate that the fundamental approach is very promising, but additional effort in experimental realization is needed.

42 ENGINEERING↗
NASA NTRS1965

Transistor voltage comparator performs own sensing

Detection of the highest voltage input among a group of varying voltage inputs is accomplished by a transistorized voltage comparison circuit. The collector circuits of the transistors perform the sensing function. Input voltage levels are governed by the transistors.

Cliff, R. A.↗
NASA NTRS1965

Simple circuit reduces transistor switching time

Silicon-Controlled Rectifier /SCR/, gated by a voltage divider, controls the potentiometer in transistorized switching circuits. The SCR acts as a gate to trigger the switching transistor only when the input signal reaches an amplitude that will switch the transistor rapidly.

Source record↗
NASA NTRS1966

Improved chopper circuit uses parallel transistors

Parallel transistor chopper circuit operates with one transistor in the forward mode and the other in the inverse mode. By using this method, it acts as a single, symmetrical, bidirectional transistor, and reduces and stabilizes the offset voltage.

Source record↗
NASA NTRS1966

Metal Oxide Silicon /MOS/ transistors protected from destructive damage by wire

Loop of flexible, small diameter, nickel wire protects metal oxide silicon /MOS/ transistors from a damaging electrostatic potential. The wire is attached to a music-wire spring, slipped over the MOS transistor case, and released so the spring tensions the wire loop around all the transistor leads, shorting them together. This allows handling without danger of damage.

Deboo, G. J.↗
NASA NTRS1973

Coaxial inverted geometry transistor having buried emitter

The invention relates to an inverted geometry transistor wherein the emitter is buried within the substrate. The transistor can be fabricated as a part of a monolithic integrated circuit and is particularly suited for use in applications where it is desired to employ low actuating voltages. The transistor may employ the same doping levels in the collector and emitter, so these connections can be reversed.

Hruby, R. J.↗
NASA NTRS1976

Modeling of short channel MOS transistors

Higher frequency response in MOS technology can be obtained by shortening the channel length. One approach for doing this involves an employment of higher resolution lithography technology. A second approach makes use of a double-diffused MOS transistor (DMOS). It is pointed out that the ordinary method of modeling the transistors used in both approaches is not accurate. An investigation is conducted of the questions which have to be considered for DMOS modeling. The modeling of a short channel MOS transistor is discussed, taking into account the derivation of the threshold voltage equation. Excellent agreement between theoretical and experimental data shows the accuracy of the described modeling approach.

Lin, H. C.↗
NASA NTRS1979

High-Speed, high-power, switching transistor

Silicon transistor rate for 200 angstroms at 400 to 600 volts combines switching speed of transistors with ruggedness, power capacity of thyristor. Transistor introduces unique combination of increased power-handling capability, unusally low saturation and switching losses, and submicrosecond switching speeds. Potential applications include high power switching regulators, linear amplifiers, chopper controls for high frequency electrical vehicle drives, VLF transmitters, RF induction heaters, kitchen cooking ranges, and electronic scalpels for medical surgery.

Carnahan, D.↗
NASA NTRS1981

Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators

Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

Doerbeck, F. H.↗
NASA NTRS1981

A gallium phosphide high-temperature bipolar junction transistor

Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

Zipperian, T. E.↗
NASA NTRS1981

High voltage power transistor development

Design considerations, fabrication procedures, and methods of evaluation for high-voltage power-transistor development are discussed. Technique improvements such as controlling the electric field at the surface and perserving lifetimes in the collector region which have advanced the state of the art in high-voltage transistors are discussed. These improvements can be applied directly to the development of 1200 volt, 200 ampere transistors.

Hower, P. L.↗
NASA NTRS1982

Transistorized PWM inverter-induction motor drive system

This paper describes the development of a transistorized PWM inverter-induction motor traction drive system. A vehicle performance analysis was performed to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of inverter and motor specifications. The inverter was a transistorized three-phase bridge using General Electric power Darlington transistors. The description of the design and development of this inverter is the principal object of this paper. The high-speed induction motor is a design which is optimized for use with an inverter power source. The primary feedback control is a torque angle control with voltage and torque outer loop controls. A current-controlled PWM technique is used to control the motor voltage. The drive has a constant torque output with PWM operation to base motor speed and a constant horsepower output with square wave operation to maximum speed. The drive system was dynamometer tested and the results are presented.

Peak, S. C.↗
NASA NTRS1986

Theoretical values of various parameters in the Gummel-Poon model of a bipolar junction transistor

Various parameters in the Gummel-Poon model of a bipolar junction transistor are expressed in terms of the basic structure of a transistor. A consistent theoretical approach is used which facilitates an understanding of the foundations and limitations of the derived formulas. The results enable one to predict how changes in the geometry and composition of a transistor would affect performance.

Benumof, R.↗
NASA NTRS1989

Calculation of the electron wave function in a graded-channel double-heterojunction modulation-doped field-effect transistor

Three double-heterojunction modulation-doped field-effect transistor structures with different channel composition are investigated theoretically. All of these transistors have an In(x)Ga(1-x)As channel sandwiched between two doped Al(0.3)Ga(0.7)As barriers with undoped spacer layers. In one of the structures, x varies from 0 from either heterojunction to 0.15 at the center of the channel quadratically; in the other two, constant values of x of 0 and 0.15 are used. The Poisson and Schroedinger equations are solved self-consistently for the electron wave function in all three cases. The results showed that the two-dimensional electron gas (2DEG) concentration in the channel of the quadratically graded structure is higher than the x = 0 one and slightly lower than the x = 0.15 one, and the mean distance of the 2DEG is closer to the center of the channel for this transistor than the other two. These two effects have important implications on the electron mobility in the channel.

Mui, D. S. L.↗
NASA NTRS1992

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

Cunningham, Thomas J.↗
NASA NTRS2004

High Electron Mobility Transistor Structures on Sapphire Substrates Using CMOS Compatible Processing Techniques

System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced electron mobility as well as the processes that limit mobility, and will be presented.

Mueller, Carl↗