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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Commercial sensor survey status report

The NEPP FY07 Sensor Technology Commercial Sensor Survey task is geared toward benefiting future NASA space missions with low-cost, short-duty-cycle, visible imaging needs. Such applications could include imaging for educational outreach purposes or short surveys of spacecraft, planetary, or lunar surfaces. Under the task, inexpensive commercial grade sensors (e.g., CMOS-based “camera on a chip” systems) have been surveyed and selected for ionizing dose and displacement damage tolerance testing. Only inexpensive, commercial imagers with potential for use in low-duty-cycle space exploration applications have been considered; the task does not address high-cost science grade imagers or hardened technologies. The selected sensors had to meet selection criteria geared toward supporting small, low-mass cameras that produce good resolution color images. This document discusses the selection process.

Konefat, Edward H.↗
NASA NTRS2015

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

14nm↗
NASA NTRS1986

A system for the functional testing and simulation of custom and semicustom VLSI chips

A system for the functional testing and simulation of custom and semicustom very large scale integrated (VLSI) chips that are designed using the integrated UNIX-based computer-aided design (CAD) system is described. The testing and simulation system consists of two parts. One of these is a special purpose hardware device that is capable of controlling the digital imputs and outputs on a custom chip. This device, the Digital Microcircuit Functionality Tester (DMFT) system, can be operated by itself or in conjunction with the VAX host computer on the CAD system. The DMFT is integrated into a microprobe station so that these signals can be injected or read from nodes inside the chip, as well as at the pins. The second part of the system is a software package that is installed on the VAX. This software package, logic, includes a full-screen editor for developing chip test sequences and drivers for both the DMFT and the esim logic simulator.

Olson, E. M.↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
NASA NTRS2001

Miniature Free-Flying Magnetometer Utilizing System-On-A-Chip Technology

Four Free-Flying Magnetometers (FFMs), developed at the Jet Propulsion Laboratory (JPL) for the Enstrophy mission, were successfully deployed from the payload of a sounding rocket launched from Poker Flats, Alaska on February 11, 1999. The FFMs functioned successfully by synchronously measuring the vector magnetic field at 4 points separate from the payload and at relative distances up to 3 km, and communicated their data, in bursts, to the ground. This is the first time synchronized in-situ multipoint measurements of the Earth's magnetic field utilizing miniature spin-stabilized "sensorcraft" have been performed. The data they provided have enabled, for the first time, the direct measure of field-aligned current density and are enabling new science by determining the fine-scale structure of the currents in the Earth's ionosphere involved in the production of aurora. These proof-of-concept "hockey puck" (80 mm diameter, 38 mm height, 250 gram mass) FFMs were built using off-the-shelf commercial, industrial, and military grade surface-mount electronic components. Radiation-hard electronics was not required for the Enstrophy mission's short sub-orbital flight. The successful design, implementation, and flight demonstration of this 1st generation FFM design has provided a solid base for further development of a 2nd generation FFM design for planetary science applications. A reliable ultra-miniature radiation-hard 2nd-generation FFM utilizing System-On-A-Chip (SOAC) technologies is proposed. This design would be targeted for long-term planetary missions to investigate magnetospheric field configurations in regions having small-scale structure and to separate spatial and temporal variations. A fleet of short-lived (expendable) FFMs would be deployed into a targeted region to gather multiprobe vector magnetic field data. The FFMs would be ejected from a parent spacecraft at a speed of a few m/sec and would cover spatial volumes of order tens of kilometers for times of order one hour. The parent spacecraft would carry a sufficient number of FFMs for multiple deployments. Additional information is contained in the original extended abstract.

Eyre, F. B.↗
NASA NTRS1999

Avionics Systems On A Chip for Space Exploration

The advanced miniaturization of all the on-board spacecraft functions into a highly integrated, modular, and reliable architecture is a major enabling technology for future deep-space and Earth orbiting science missions.

Avionics↗
NASA NTRS2007

A One Chip Hardened Solution for High Speed SpaceWire System Implementations. Session: Components

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASIC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a router with 4 SpaceWire ports and two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, and a memory controller for additional external memory use. The SpaceWire cores are also reused in other ASICs under development. The SpaceWire ASIC is planned for use on the Geostationary Operational Environmental Satellites (GOES)-R, the Lunar Reconnaissance Orbiter (LRO) and other missions. Engineering and flight parts have been delivered to programs and users. This paper reviews the SpaceWire protocol and those elements of it that have been built into the current and next SpaceWire reusable cores and features within the core that go beyond the current standard and can be enabled or disabled by the user. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be reviewed and highlighted. Optional configurations within user systems and test boards will be shown. The physical implementation of the design will be described and test results from the hardware will be discussed. Application of this ASIC and other ASICs containing the SpaceWire cores and embedded microcontroller to Plug and Play and reconfigurable implementations will be described. Finally, the BAE Systems roadmap for SpaceWire developments will be updated, including some products already in design as well as longer term plans.

Marshall, Joseph R.↗
NASA NTRS2017

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

single event effect (SEE)↗
NASA NTRS1995

Compact Multimedia Systems in Multi-chip Module Technology

This tutorial paper shows advanced multimedia system designs based on multi-chip module (MCM) technologies that provide essential computing, compression, communication, and storage capabilities for various large scale information highway applications.!.

Multi-Chip Module Technology↗
DOE OSTI2024

Scalable DAQ system operating the CHIPS-5 neutrino detector

The CHIPS R&D project focuses on development of low-cost water Cherenkov neutrino detectors through novel design strategies and resourceful engineering. This work presents an end-to-end DAQ solution intended for a recent 5 kt CHIPS prototype, which is largely based on affordable mass-produced components. Much like the detector itself, the presented instrumentation is composed of modular arrays that can be scaled up and easily serviced. A single such array can carry up to 30 photomultiplier tubes (PMTs) accompanied by electronics that generate high voltage in-situ and deliver time resolution of up to 0.69 ns. In addition, the technology is compatible with the White Rabbit timing system, which can synchronize its elements to within 100 ps. While deployment issues did not permit the presented DAQ system to operate beyond initial evaluation, the presented hardware and software successfully passed numerous commissioning tests that demonstrated their viability for use in a large-scale neutrino detector, instrumented with thousands of PMTs.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1985

A laser plotting system for VLSI chip layouts

One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

Deutsch, L. J.↗