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All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Trellises and Trellis-Based Decoding Algorithms for Linear Block Codes

A code trellis is a graphical representation of a code, block or convolutional, in which every path represents a codeword (or a code sequence for a convolutional code). This representation makes it possible to implement Maximum Likelihood Decoding (MLD) of a code with reduced decoding complexity. The most well known trellis-based MLD algorithm is the Viterbi algorithm. The trellis representation was first introduced and used for convolutional codes [23]. This representation, together with the Viterbi decoding algorithm, has resulted in a wide range of applications of convolutional codes for error control in digital communications over the last two decades. There are two major reasons for this inactive period of research in this area. First, most coding theorists at that time believed that block codes did not have simple trellis structure like convolutional codes and maximum likelihood decoding of linear block codes using the Viterbi algorithm was practically impossible, except for very short block codes. Second, since almost all of the linear block codes are constructed algebraically or based on finite geometries, it was the belief of many coding theorists that algebraic decoding was the only way to decode these codes. These two reasons seriously hindered the development of efficient soft-decision decoding methods for linear block codes and their applications to error control in digital communications. This led to a general belief that block codes are inferior to convolutional codes and hence, that they were not useful. Chapter 2 gives a brief review of linear block codes. The goal is to provide the essential background material for the development of trellis structure and trellis-based decoding algorithms for linear block codes in the later chapters. Chapters 3 through 6 present the fundamental concepts, finite-state machine model, state space formulation, basic structural properties, state labeling, construction procedures, complexity, minimality, and sectionalization of trellises. Chapter 7 discusses trellis decomposition and subtrellises for low-weight codewords. Chapter 8 first presents well known methods for constructing long powerful codes from short component codes or component codes of smaller dimensions, and then provides methods for constructing their trellises which include Shannon and Cartesian product techniques. Chapter 9 deals with convolutional codes, puncturing, zero-tail termination and tail-biting.Chapters 10 through 13 present various trellis-based decoding algorithms, old and new. Chapter 10 first discusses the application of the well known Viterbi decoding algorithm to linear block codes, optimum sectionalization of a code trellis to minimize computation complexity, and design issues for IC (integrated circuit) implementation of a Viterbi decoder. Then it presents a new decoding algorithm for convolutional codes, named Differential Trellis Decoding (DTD) algorithm. Chapter 12 presents a suboptimum reliability-based iterative decoding algorithm with a low-weight trellis search for the most likely codeword. This decoding algorithm provides a good trade-off between error performance and decoding complexity. All the decoding algorithms presented in Chapters 10 through 12 are devised to minimize word error probability. Chapter 13 presents decoding algorithms that minimize bit error probability and provide the corresponding soft (reliability) information at the output of the decoder. Decoding algorithms presented are the MAP (maximum a posteriori probability) decoding algorithm and the Soft-Output Viterbi Algorithm (SOVA) algorithm. Finally, the minimization of bit error probability in trellis-based MLD is discussed.

Lin, Shu↗
NASA NTRS2008

Runtime Verification of C Programs

We present in this paper a framework, RMOR, for monitoring the execution of C programs against state machines, expressed in a textual (nongraphical) format in files separate from the program. The state machine language has been inspired by a graphical state machine language RCAT recently developed at the Jet Propulsion Laboratory, as an alternative to using Linear Temporal Logic (LTL) for requirements capture. Transitions between states are labeled with abstract event names and Boolean expressions over such. The abstract events are connected to code fragments using an aspect-oriented pointcut language similar to ASPECTJ's or ASPECTC's pointcut language. The system is implemented in the C analysis and transformation package CIL, and is programmed in OCAML, the implementation language of CIL. The work is closely related to the notion of stateful aspects within aspect-oriented programming, where pointcut languages are extended with temporal assertions over the execution trace.

RMOR↗
NASA NTRS2010

Proceedings of the Second NASA Formal Methods Symposium

This publication contains the proceedings of the Second NASA Formal Methods Symposium sponsored by the National Aeronautics and Space Administration and held in Washington D.C. April 13-15, 2010. Topics covered include: Decision Engines for Software Analysis using Satisfiability Modulo Theories Solvers; Verification and Validation of Flight-Critical Systems; Formal Methods at Intel -- An Overview; Automatic Review of Abstract State Machines by Meta Property Verification; Hardware-independent Proofs of Numerical Programs; Slice-based Formal Specification Measures -- Mapping Coupling and Cohesion Measures to Formal Z; How Formal Methods Impels Discovery: A Short History of an Air Traffic Management Project; A Machine-Checked Proof of A State-Space Construction Algorithm; Automated Assume-Guarantee Reasoning for Omega-Regular Systems and Specifications; Modeling Regular Replacement for String Constraint Solving; Using Integer Clocks to Verify the Timing-Sync Sensor Network Protocol; Can Regulatory Bodies Expect Efficient Help from Formal Methods?; Synthesis of Greedy Algorithms Using Dominance Relations; A New Method for Incremental Testing of Finite State Machines; Verification of Faulty Message Passing Systems with Continuous State Space in PVS; Phase Two Feasibility Study for Software Safety Requirements Analysis Using Model Checking; A Prototype Embedding of Bluespec System Verilog in the PVS Theorem Prover; SimCheck: An Expressive Type System for Simulink; Coverage Metrics for Requirements-Based Testing: Evaluation of Effectiveness; Software Model Checking of ARINC-653 Flight Code with MCP; Evaluation of a Guideline by Formal Modelling of Cruise Control System in Event-B; Formal Verification of Large Software Systems; Symbolic Computation of Strongly Connected Components Using Saturation; Towards the Formal Verification of a Distributed Real-Time Automotive System; Slicing AADL Specifications for Model Checking; Model Checking with Edge-valued Decision Diagrams; and Data-flow based Model Analysis.

Munoz, Cesar↗
NASA NTRS2004

Transitioning from Software Requirements Models to Design Models

The Scenario Creation and Simulation Process (SCASP) includes the following steps: 1) Write Requirements; 2) Write Use Cases; 3) Prioritize Use Cases; 4) Write Nominal Scenarios; 5) Identify Relationships; 6) Refine/Generalize Scenarios; 7) Transform to State Machines. SCASP provides thorough simulation of use cases before design/implementation, resulting in: 1) Reduced cost; 2) Fewer misunderstandings; 3) Reuse of executable form of use cases. SCASP gives systematic guidelines on how to 1) Separate concerns in use case descriptions; 2) Elicit non-nominal scenarios (alternatives, exceptions, concurrent scenarios, etc.); 3) Transform those scenarios automatically into a set of concurrent state machines; 4) Execute those state machines, i.e., scenario simulation.

Whittle, Jon↗
NASA NTRS2004

A 2-to-48-MHz Phase-Locked Loop

A 2-to-48-MHz phase-locked loop (PLL), developed for the U.S. space program, meets or exceeds all space shuttle clock electrical interface requirements by taking as its reference a 2-to-48-MHz clock signal and outputting a phaselocked clock signal set at the same frequency as the reference clock with transistor- transistor logic (TTL) voltage levels. Because it is more adaptable than other PLLs, the new PLL can be used in industries that employ signaling devices and as a tool in future space missions. A conventional PLL consists of a phase/frequency detector, loop filter, and voltage-controlled oscillator in which each component exists individually and is integrated into a single device. PLL components phase-lock to a single frequency or to a narrow bandwidth of frequencies. It is this design, however, that prohibits them from maintaining phase lock to a dynamically changing reference clock when a large bandwidth is required a deficiency the new PLL overcomes. Since most PLL components require their voltage-controlled oscillators to operate at greater than 2-MHz frequencies, conventional PLLs often cannot achieve the low-frequency phase lock allowed by the new PLL. The 2-to-48-MHz PLL is built on a wire-wrap board with pins wired to three position jumpers; this makes changing configurations easy. It responds to variations in voltage-controlled oscillator (VCO) ranges, duty cycle, signal-to-noise ratio (SNR), amplitude, and jitter, exceeding design specifications. A consensus state machine, implemented in a VCO range detector which assures the PLL continues to operate in the correct range, is the primary control state machine for the 2-to-48-MHz PLL circuit. By using seven overlapping frequency ranges with hysteresis, the PLL output sets the resulting phase-locked clock signal at a frequency that agrees with the reference clock with TTL voltage levels. As a space-shuttle tool, the new PLL circuit takes the noisy, degraded reference clock signals as input and outputs phase-locked clock signals of the same frequency but with a corrected wave shape. Since its configuration circuit can be easily changed, the new PLL can do the following: readily respond to variations in VCO ranges, duty cycle, SNR, amplitude, and jitter; continuously operate in the correct VCO range because of its consensus state machine; and use its range detector implements to overlap seven frequency ranges with hysteresis, thus giving the current design a flexibility that exceeds anything available at the time of this development. These features will benefit any industry in which safe and timely clock signals are vital to operation.

Koudelka, Robert D.↗
NASA NTRS2017

Generating Real-Time Robotics Control Software from SysML

In this paper, we outline an approach for autogenerating real-time robotics control code from hierarchical state machines and hardware configurations encoded in Systems Modeling Language (SysML). We propose a software architecture that provides an abstract SysML layer with access to device state information and a set of primitive device commands, such as move actuator and release brake, allowing a user to build up a complete functional state machine directly in SysML. The SysML diagram is then exported to a standard SCXML file format and subsequently used to auto-generate hardware control code. Once this architecture is in place, the only explicit code elements that need to be written are the primitive device commands, which can be easily unit tested and reused across different systems. The motivation for this work was the need for a test bed that enables the rapid prototyping of mechanisms and control algorithms for a spacecraft that could ultimately be used for preparing Martian rock samples for their return to Earth. To this end, our software system was also designed to allow for the run-time specification of the hardware layout in SysML, with the hardware-level control functions kept agnostic to the specific parameters or communication bus of any particular device. Further, we outline a system for specifying both the state machine and hardware configuration in the MagicDraw IDE in such a way that the system can be simulated before any code is generated. The resultant software system is easy to debug, understand, and allows users to choose how much information is encoded as a visual or text-based representation.

Godart, Peter↗
NASA NTRS2006

Programmable Pulse-Position-Modulation Encoder

A programmable pulse-position-modulation (PPM) encoder has been designed for use in testing an optical communication link. The encoder includes a programmable state machine and an electronic code book that can be updated to accommodate different PPM coding schemes. The encoder includes a field-programmable gate array (FPGA) that is programmed to step through the stored state machine and code book and that drives a custom high-speed serializer circuit board that is capable of generating subnanosecond pulses. The stored state machine and code book can be updated by means of a simple text interface through the serial port of a personal computer.

Zhu, David↗
NASA NTRS1992

Intelligent fuzzy controller for event-driven real time systems

Most of the known linguistic models are essentially static, that is, time is not a parameter in describing the behavior of the object's model. In this paper we show a model for synchronous finite state machines based on fuzzy logic. Such finite state machines can be used to build both event-driven, time-varying, rule-based systems and the control unit section of a fuzzy logic computer. The architecture of a pipelined intelligent fuzzy controller is presented, and the linguistic model is represented by an overall fuzzy relation stored in a single rule memory. A VLSI integrated circuit implementation of the fuzzy controller is suggested. At a clock rate of 30 MHz, the controller can perform 3 MFLIPS on multi-dimensional fuzzy data.

Grantner, Janos↗
NASA NTRS1990

Decidability for a temporal logic used in discrete-event system analysis

The type of plant considered is one that can be modeled by a nondeterministic finite-state machine P. The regulator is a deterministic finite state machine R. The closed-loop system is formed by connecting P and R in a regulator configuration. Formulas in a propositional temporal language are used to describe the behavior of the closed-loop system. It is shown that there is a mechanical procedure which, for a given P and R, and a temporal formula Psi, will determine in a finite number of steps whether or not Psi must be true. This 'decidability' result could be proven using other known results on temporal logic. The proof given here shows that the behavior of the closed-loop system may safely be assumed to be ultimately periodic. The results are illustrated on two discrete-event system examples.

Knight, J. F.↗
NASA NTRS2019

Onboard Decision-Making for Nominal and Contingency sUAS Flight

This study presents an onboard decision-making architecture for small unmanned aerial systems (sUAS). The decision-maker is part of NASA's SAFE50 project that is working under the UAS Traffic Management (UTM) Technical Capability Level (TCL) 4 to provide autonomous point-to-point UAV flight in BVLOS, high-density urban environments. The decision-maker monitors various metrics to determine the safety and feasibility of the mission and categorizes flight states as Nominal, Off-Nominal, Alternate Land, and Land Now in a finite state machine. Changes in the monitored metrics serve as transitions in the state machine and trigger replanning. Navigation degradation and communication failure are simulated to show the feasibility of the decision-maker framework in appropriately switching the flight state.

Baculi, Joshua↗
NASA NTRSDate not supplied

Predicting Cognitive States Using Machine Learning Fusion Paradigms to Reduce Model Uncertainty

The development of a synergetic system between humans and technology is a challenge that the scientific community has been facing for many years. Our aeronautic research aims to enhance this synergy between humans and machines through predictive human performance modeling for systems to mitigate high-risk situations. By being able to predict and anticipate human states, the crew monitoring system should be able to adjust and support the pilot for aviation safety. Our work focusing on attention-related human performance-limiting states (AHPLS) that impact a pilot’s performance and introduce high-risk catastrophic situations [1]. For example, AHPLS has been cited as a causal factor in more than 50% of all loss control in flight and thus contributes significantly toward commercial aviation fatalities [1, 2]. Cognitive state and its physiological fingerprint can be valuable information for this detecting AHPLS, but human cognitive state detection is still a major limitation for these crew monitoring systems.

machine learning↗
NASA NTRS1981

Development techniques for generic software

In developing the first version of a generic implementation of X.25, Levels 2 and 3, three development techniques are examined: table driven finite state machine implementation, an integrated testing environment, and top down design. A finite state machine (FSM) is a powerful tool for both specifying and implementing protocols. This technique was used in the X.25 specification. A table driven implementation of the FSM was chosen to facilitate changes and simplify coding. The effect that this technique have on program size, speed of execution, coding time, and debugging time are investigated.

Hamilton, R. L.↗
NASA NTRS1989

Pass-transistor asynchronous sequential circuits

Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N + M times.

Whitaker, Sterling R.↗
NASA NTRS1990

A programmable architecture for CMOS sequential circuits

This paper presents a programmable architecture for sequential pass transistor circuits. The resulting circuits are such that a state machine with N states and M output is constructed using a single layout replicated N + M times.

Whitaker, S.↗
NASA NTRS2013

FPGA-Based X-Ray Detection and Measurement for an X-Ray Polarimeter

This technology enables detection and measurement of x-rays in an x-ray polarimeter using a field-programmable gate array (FPGA). The technology was developed for the Gravitational and Extreme Magnetism Small Explorer (GEMS) mission. It performs precision energy and timing measurements, as well as rejection of non-x-ray events. It enables the GEMS polarimeter to detect precisely when an event has taken place so that additional measurements can be made. The technology also enables this function to be performed in an FPGA using limited resources so that mass and power can be minimized while reliability for a space application is maximized and precise real-time operation is achieved. This design requires a low-noise, charge-sensitive preamplifier; a highspeed analog to digital converter (ADC); and an x-ray detector with a cathode terminal. It functions by computing a sum of differences for time-samples whose difference exceeds a programmable threshold. A state machine advances through states as a programmable number of consecutive samples exceeds or fails to exceed this threshold. The pulse height is recorded as the accumulated sum. The track length is also measured based on the time from the start to the end of accumulation. For track lengths longer than a certain length, the algorithm estimates the barycenter of charge deposit by comparing the accumulator value at the midpoint to the final accumulator value. The design also employs a number of techniques for rejecting background events. This innovation enables the function to be performed in space where it can operate autonomously with a rapid response time. This implementation combines advantages of computing system-based approaches with those of pure analog approaches. The result is an implementation that is highly reliable, performs in real-time, rejects background events, and consumes minimal power.

Gregory, Kyle↗
NASA NTRS2008

Aspect-Oriented Monitoring of C Programs

The paper presents current work on extending ASPECTC with state machines, resulting in a framework for aspect-oriented monitoring of C programs. Such a framework can be used for testing purposes, or it can be part of a fault protection strategy. The long term goal is to explore the synergy between the fields of runtime verification, focused on program monitoring, and aspect-oriented programming, focused on more general program development issues. The work is inspired by the observation that most work in this direction has been done for JAVA, partly due to the lack of easily accessible extensible compiler frameworks for C. The work is performed using the SILVER extensible attribute grammar compiler framework, in which C has been defined as a host language. Our work consists of extending C with ASPECTC, and subsequently to extend ASPECTC with state machines.

runtime verifications↗
NASA NTRS2017

Pulse Generator

An apparatus and a computer-implemented method for generating pulses synchronized to a rising edge of a tachometer signal from rotating machinery are disclosed. For example, in one embodiment, a pulse state machine may be configured to generate a plurality of pulses, and a period state machine may be configured to determine a period for each of the plurality of pulses.

Greer, Lawrence↗