SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Thin layer of platinum or other high-work-function metal applied to back side of rear-illuminated charge-coupled device (CCD) achieves quantum efficiency (QE)-pinned state, an ideal condition allowing sensor to achieve 100-percent internal charge-collection efficiency within its photosensitive volume. Metal layer, called flash gate, easily applied by tungsten vacuum deposition during last step of sensor fabrication.
A strong pulsation event was observed in the magnetosphere near L = 5 with the flux gate magnetometer on Explorer 45. The event occurred near 2300 UT on June 18, 1972, during the recovery phase of a large magnetic storm. Explorer 45 was in the afternoon quadrant, and the event was also observed at many day side, ground level observatories at high and low latitudes. The event had a complex spectrum with distinct pulsations near 2, 6, and 14 mHz (500-, 160-, and 70-s periods). The two lower-frequency pulsations were also observed on the ground. A comparison of the frequencies and polarizations of satellite and ground observations indicates that the event was similar to events observed recently along a latitudinal chain of ground stations in Canada.
The FIELDS instrumentation suite on the Magnetospheric Multiscale (MMS) mission provides comprehensive measurements of the full vector magnetic and electric fields in the reconnection regions investigated by MMS, including the dayside magnetopause and the night-side magnetotail acceleration regions out to 25 Re. Six sensors on each of the four MMS spacecraft provide overlapping measurements of these fields with sensitive cross-calibrations both before and after launch. The FIELDS magnetic sensors consist of redundant flux-gate magnetometers (AFG and DFG) over the frequency range from DC to 64 Hz, a search coil magnetometer (SCM) providing AC measurements over the full whistler mode spectrum expected to be seen on MMS, and an Electron Drift Instrument (EDI) that calibrates offsets for the magnetometers. The FIELDS three-axis electric field measurements are provided by two sets of biased double-probe sensors (SDP and ADP) operating in a highly symmetric spacecraft environment to reduce significantly electrostatic errors. These sensors are complemented with the EDI electric measurements that are free from all local spacecraft perturbations. Cross-calibrated vector electric field measurements are thus produced from DC to 100 kHz, well beyond the upper hybrid resonance whose frequency provides an accurate determination of the local electron density. Due to its very large geometric factor, EDI also provides very high time resolution (∼1 ms) ambient electron flux measurements at a few selected energies near 1 keV. This paper provides an overview of the FIELDS suite, its science objectives and measurement requirements, and its performance as verified in calibration and cross-calibration procedures that result in anticipated errors less than 0.1 nT in B and 0.5 mV/m in E. Summaries of data products that result from FIELDS are also described, as well as algorithms for cross-calibration. Details of the design and performance characteristics of AFG/DFG, SCM, ADP, SDP, and EDI are provided in five companion papers.
A clamp-mount device is disclosed for mounting equipment to an associated I-beam and the like structural member of the type having oppositely extending flanges wherein the device comprises a base and a pair of oppositely facing clamping members carried diagonally on the base clamping flanges therebetween and having flange receiving openings facing one another. Lock means are carried diagonally by the base opposite the clamping members locking the flanges in the clamping members. A resilient hub is carried centrally of the base engaging and biasing a back side of the flanges maintaining tightly clamped and facilitating use on vertical as well as horizontal members. The base turns about the hub to receive the flanges within the clamping members. Equipment may be secured to the base by any suitable means such as bolts in openings. Slidable gate latches secure the hinged locks in an upright locking position. The resilient hub includes a recess opening formed in the base and a rubber-like pad carried in this opening being depressably and rotatably carried therein.
The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.
Topics covered include: Fused Reality for Enhanced Flight Test Capabilities; Thermography to Inspect Insulation of Large Cryogenic Tanks; Crush Test Abuse Stand; Test Generator for MATLAB Simulations; Dynamic Monitoring of Cleanroom Fallout Using an Air Particle Counter; Enhancement to Non-Contacting Stress Measurement of Blade Vibration Frequency; Positively Verifying Mating of Previously Unverifiable Flight Connectors; Radiation-Tolerant Intelligent Memory Stack - RTIMS; Ultra-Low-Dropout Linear Regulator; Excitation of a Parallel Plate Waveguide by an Array of Rectangular Waveguides; FPGA for Power Control of MSL Avionics; UAVSAR Active Electronically Scanned Array; Lockout/Tagout (LOTO) Simulator; Silicon Carbide Mounts for Fabry-Perot Interferometers; Measuring the In-Process Figure, Final Prescription, and System Alignment of Large; Optics and Segmented Mirrors Using Lidar Metrology; Fiber-Reinforced Reactive Nano-Epoxy Composites; Polymerization Initiated at the Sidewalls of Carbon Nanotubes; Metal-Matrix/Hollow-Ceramic-Sphere Composites; Piezoelectrically Enhanced Photocathodes; Iridium-Doped Ruthenium Oxide Catalyst for Oxygen Evolution; Improved Mo-Re VPS Alloys for High-Temperature Uses; Data Service Provider Cost Estimation Tool; Hybrid Power Management-Based Vehicle Architecture; Force Limit System; Levitated Duct Fan (LDF) Aircraft Auxiliary Generator; Compact, Two-Sided Structural Cold Plate Configuration; AN Fitting Reconditioning Tool; Active Response Gravity Offload System; Method and Apparatus for Forming Nanodroplets; Rapid Detection of the Varicella Zoster Virus in Saliva; Improved Devices for Collecting Sweat for Chemical Analysis; Phase-Controlled Magnetic Mirror for Wavefront Correction; and Frame-Transfer Gating Raman Spectroscopy for Time-Resolved Multiscalar Combustion Diagnostics.
A prototype small, lightweight micro Sun sensor (MSS) has been flight qualified as part of the attitude-determination system of a spacecraft or for Mars surface operations. The MSS has previously been reported at a very early stage of development in NASA Tech Briefs, Vol. 28, No. 1 (January 2004). An MSS is essentially a miniature multiple-pinhole electronic camera combined with digital processing electronics that functions analogously to a sundial. A micromachined mask containing a number of microscopic pinholes is mounted in front of an active-pixel sensor (APS). Electronic circuits for controlling the operation of the APS, readout from the pixel photodetectors, and analog-to-digital conversion are all integrated onto the same chip along with the APS. The digital processing includes computation of the centroids of the pinhole Sun images on the APS. The spacecraft computer has the task of converting the Sun centroids into Sun angles utilizing a calibration polynomial. The micromachined mask comprises a 500-micron-thick silicon wafer, onto which is deposited a 57-nm-thick chromium adhesion- promotion layer followed by a 200-nm-thick gold light-absorption layer. The pinholes, 50 microns in diameter, are formed in the gold layer by photolithography. The chromium layer is thin enough to be penetrable by an amount of Sunlight adequate to form measurable pinhole images. A spacer frame between the mask and the APS maintains a gap of .1 mm between the pinhole plane and the photodetector plane of the APS. To minimize data volume, mass, and power consumption, the digital processing of the APS readouts takes place in a single field-programmable gate array (FPGA). The particular FPGA is a radiation- tolerant unit that contains .32,000 gates. No external memory is used so the FPGA calculates the centroids in real time as pixels are read off the APS with minimal internal memory. To enable the MSS to fit into a small package, the APS, the FPGA, and other components are mounted on a single two-sided board following chip-on-board design practices
The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm.
An arrangement for butt-welding cylindrical sections of large, thin-wall tanks includes a rotatable mandrel with side-by-side sets of radial position adjusters. Each set of adjusters bears on one of the tank sections adjacent the seam, to prevent the sections from sagging out-of-round. The mandrel rotates relative to the welder, so that a continuous seam is formed. A purge chamber is fixed in position behind the seam at the weld head, and is flushed with inert gas. The purge chamber includes a two-sided structure which is contiguous with the cylindrical sections and a circumferential vane to form an open-ended tube-like structure, through which the radial position adjusters pass as the mandrel and cylindrical workpiece sections rotate. The tube-like structure is formed into a chamber by a plurality of movable gates which are controlled to maintain a seal while allowing adjusters to progress through the purge chamber.
This paper describes development of a radiation tolerant, low power, reconfigurable avionics module aimed at meeting the avionics needs of the JPL Micro-Inspector spacecraft. This module represents a complete avionics system, consisting of two PowerPC 405 CPUs embedded within a reconfigurable FPGA fabric of over 8 Million logic gates, 64MB of EDAC protected Flash storage and 128MB of EDAC protected DDR SDRAM or SDRAM memories, along with FPGA SEU mitigation logic, and all necessary power conversion. Processor SEU mitigation is achieved by running the two processors in a lock-step and compare configuration. All of these building blocks are integrated into a double sided circuit board that takes as little as 6 square inches of board space. This module can be embedded into a user system as part of a bigger circuit assembly or as a self contained module. This module is being developed as part of a JPL led Micro-Inspector Program, funded by NASA ESMD aimed at producing a 10Kg micro spacecraft.
This work addresses distributed data management and access dynamically configurable high-speed access to data distributed and shared over wide-area high-speed network environments. An offload engine NIC (network interface card) is proposed that scales at nX10-Gbps increments through 100-Gbps full duplex. The Globus de facto standard was used in projects requiring secure, robust, high-speed bulk data transport. Novel extension mechanisms were derived that will combine these technologies for use by GridFTP, bandwidth management resources, and host CPU (central processing unit) acceleration. The result will be wire-rate encrypted Globus grid data transactions through offload for splintering, encryption, and compression. As the need for greater network bandwidth increases, there is an inherent need for faster CPUs. The best way to accelerate CPUs is through a network acceleration engine. Grid computing data transfers for the Globus tool set did not have wire-rate encryption or compression. Existing technology cannot keep pace with the greater bandwidths of backplane and network connections. Present offload engines with ports to Ethernet are 32 to 40 Gbps f-d at best. The best of ultra-high-speed offload engines use expensive ASICs (application specific integrated circuits) or NPUs (network processing units). The present state of the art also includes bonding and the use of multiple NICs that are also in the planning stages for future portability to ASICs and software to accommodate data rates at 100 Gbps. The remaining industry solutions are for carrier-grade equipment manufacturers, with costly line cards having multiples of 10-Gbps ports, or 100-Gbps ports such as CFP modules that interface to costly ASICs and related circuitry. All of the existing solutions vary in configuration based on requirements of the host, motherboard, or carriergrade equipment. The purpose of the innovation is to eliminate data bottlenecks within cluster, grid, and cloud computing systems, and to add several more capabilities while reducing space consumption and cost. Provisions were designed for interoperability with systems used in the NASA HEC (High-End Computing) program. The new acceleration engine consists of state-ofthe- art FPGA (field-programmable gate array) core IP, C, and Verilog code; novel communication protocol; and extensions to the Globus structure. The engine provides the functions of network acceleration, encryption, compression, packet-ordering, and security added to Globus grid or for cloud data transfer. This system is scalable in nX10-Gbps increments through 100-Gbps f-d. It can be interfaced to industry-standard system-side or network-side devices or core IP in increments of 10 GigE, scaling to provide IEEE 40/100 GigE compliance.
Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor.
A method for promoting quantum efficiency (QE) of a CCD imaging sensor for UV, far UV and low energy x-ray wavelengths by overthinning the back side beyond the interface between the substrate and the photosensitive semiconductor material, and flooding the back side with UV prior to using the sensor for imaging. This UV flooding promotes an accumulation layer of positive states in the oxide film over the thinned sensor to greatly increase QE for either frontside or backside illumination. A permanent or semipermanent image (analog information) may be stored in a frontside SiO.sub.2 layer over the photosensitive semiconductor material using implanted ions for a permanent storage and intense photon radiation for a semipermanent storage. To read out this stored information, the gate potential of the CCD is biased more negative than that used for normal imaging, and excess charge current thus produced through the oxide is integrated in the pixel wells for subsequent readout by charge transfer from well to well in the usual manner.
The structure of the magnetotail is investigated in a laboratory simulated magnetosphere. Particular emphasis is placed on the region of distant magnetotail where the closed field line region of the plasma sheet terminates and the process of reconnection takes place. Our study builds upon the previous investigation of the magnetotail where the main results were based on the magnetic field measurements in the tail region of the simulated magnetosphere. In this paper, more elaborate measurements of plasma flow and electric field are presented. Besides these measurements, this region of distant magnetotail is also explored by high resolution imaging with a gated optical imager (GOI) and by digital image analysis. These images clearly reveal a Y-type magnetic neutral line for the northward 'interplanetary' field (IMF) and a usual X-type for the southward IMF that confirms our previous results deduced from the magnetic field measurements. In the neighborhood of these neutral points a strong component of dawn to dusk electric field (E(sub y)) and a counterstreaming plasma flow is also observed. Plasma flow is measured by using a double sided Faraday cup which is also used to measure the y-component of tail current (J(sub y)) at different locations. These measurements reveal that the tail current is not carried by ions as previously thought, rather it is carried by electrons alone.
Electrical power and control systems designed for use in planetary exploration missions and deep space probes require electronics that are capable of efficient and reliable operation under extreme temperature conditions. In addition, space-based infrared satellites, all-electric ships, jet engines, electromagnetic launchers, magnetic levitation transport systems, and power facilities are also typical examples where system electronics are expected to be exposed to harsh temperatures and to operate under severe thermal swings. Most commercial-off-the-shelf (COTS) devices are not designed to function under such extreme conditions and very little data exist on their performance outside their specified range of operation. In this work, the performance of an ultrafast gate driver for controlling power-level transistors was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance for potential use of this device in space exploration missions under extreme temperature conditions.
The Miniaturized Electron pRoton Telescope, MERiT, is a low‐mass, low‐power, compact instrument using an innovative combination of particle detectors, sensor electronics, and onboard processing. MERiT is flying on the Compact Radiation belt Explorer, CeREs, a 3U CubeSat launched into a low earth orbit of 500‐km altitude and inclination of 85° on 16 December 2018. The primary and secondary science goals of CeREs are to investigate electron microbursts and to study solar particles. MERiT comprises a stack of solid state detectors (SSD) behind space facing avalanche photo diodes (APDs) surrounded by W‐Al shielding to reduce side‐penetrating particle background. The APD‐SSD combination enables measurement of electrons from 5 to 200 keV and 1 to 8 MeV; protons from 200–400 keV and 7–100 MeV in differential channels with energy resolution ΔE/E≈30% for both electrons and protons. MERiT measures microbursts with a high time resolution ranging from 4 to 16 ms and solar particles with a cadence of 1 s. MERiT energy channels and cadences are software configurable via algorithms and lookup tables residing on a field‐programmable gate array. The lookup tables can be changed via ground commands. MERiT geometry factor is 31 sq.cm‐sr and optimized to measure microbursts with the instrument viewing the local zenith in orbit. MERiT enables investigation of dynamical processes of radiation belt electron energization and loss, solar electron and proton transport, and their access to the Earth's polar caps. We describe the MERiT sensor design, calibration, operational modes, data products, and science goals.
This paper discusses scatterometer measurements collected with multi-mode Digital Beamforming Synthetic Aperture Radar (DBSAR) during the SMAP-VEX 2008 campaign. The 2008 SMAP Validation Experiment was conducted to address a number of specific questions related to the soil moisture retrieval algorithms. SMAP-VEX 2008 consisted on a series of aircraft-based.flights conducted on the Eastern Shore of Maryland and Delaware in the fall of 2008. Several other instruments participated in the campaign including the Passive Active L-Band System (PALS), the Marshall Airborne Polarimetric Imaging Radiometer (MAPIR), and the Global Positioning System Reflectometer (GPSR). This campaign was the first SMAP Validation Experiment. DBSAR is a multimode radar system developed at NASA/Goddard Space Flight Center that combines state-of-the-art radar technologies, on-board processing, and advances in signal processing techniques in order to enable new remote sensing capabilities applicable to Earth science and planetary applications [l]. The instrument can be configured to operate in scatterometer, Synthetic Aperture Radar (SAR), or altimeter mode. The system builds upon the L-band Imaging Scatterometer (LIS) developed as part of the RadSTAR program. The radar is a phased array system designed to fly on the NASA P3 aircraft. The instrument consists of a programmable waveform generator, eight transmit/receive (T/R) channels, a microstrip antenna, and a reconfigurable data acquisition and processor system. Each transmit channel incorporates a digital attenuator, and digital phase shifter that enables amplitude and phase modulation on transmit. The attenuators, phase shifters, and calibration switches are digitally controlled by the radar control card (RCC) on a pulse by pulse basis. The antenna is a corporate fed microstrip patch-array centered at 1.26 GHz with a 20 MHz bandwidth. Although only one feed is used with the present configuration, a provision was made for separate corporate feeds for vertical and horizontal polarization. System upgrades to dual polarization are currently under way. The DBSAR processor is a reconfigurable data acquisition and processor system capable of real-time, high-speed data processing. DBSAR uses an FPGA-based architecture to implement digitally down-conversion, in-phase and quadrature (I/Q) demodulation, and subsequent radar specific algorithms. The core of the processor board consists of an analog-to-digital (AID) section, three Altera Stratix field programmable gate arrays (FPGAs), an ARM microcontroller, several memory devices, and an Ethernet interface. The processor also interfaces with a navigation board consisting of a GPS and a MEMS gyro. The processor has been configured to operate in scatterometer, Synthetic Aperture Radar (SAR), and altimeter modes. All the modes are based on digital beamforming which is a digital process that generates the far-field beam patterns at various scan angles from voltages sampled in the antenna array. This technique allows steering the received beam and controlling its beam-width and side-lobe. Several beamforming techniques can be implemented each characterized by unique strengths and weaknesses, and each applicable to different measurement scenarios. In Scatterometer mode, the radar is capable to.generate a wide beam or scan a narrow beam on transmit, and to steer the received beam on processing while controlling its beamwidth and side-lobe level. Table I lists some important radar characteristics
It is now possible to grow silicon nanowires at chosen positions and orientations by a method that involves a combination of standard microfabrication processes. Because their positions and orientations can be chosen with unprecedented precision, the nanowires can be utilized as integral parts of individually electronically addressable devices in dense arrays. Nanowires made from silicon and perhaps other semiconductors hold substantial promise for integration into highly miniaturized sensors, field-effect transistors, optoelectronic devices, and other electronic devices. Like bulk semiconductors, inorganic semiconducting nanowires are characterized by electronic energy bandgaps that render them suitable as means of modulating or controlling electronic signals through electrostatic gating, in response to incident light, or in response to molecules of interest close to their surfaces. There is now potential for fabricating arrays of uniform, individually electronically addressable nanowires tailored to specific applications. The method involves formation of metal catalytic particles at the desired positions on a substrate, followed by heating the substrate in the presence of silane gas. The figure illustrates an example in which a substrate includes a silicon dioxide surface layer that has been etched into an array of pillars and the catalytic (in this case, gold) particles have been placed on the right-facing sides of the pillars. The catalytic thermal decomposition of the silane to silicon and hydrogen causes silicon columns (the desired nanowires) to grow outward from the originally catalyzed spots on the substrate, carrying the catalytic particles at their tips. Thus, the position and orientation of each silicon nanowire is determined by the position of its originally catalyzed spot on the substrate surface, and the orientation of the nanowire is perpendicular to the substrate surface at the originally catalyzed spot.