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At least 55 records · Page 3

Gallium Oxide Heterojunction Diodes for 400 °C High‐Temperature Applications

β ‐Ga 2 O 3 ‐based semiconductor devices are expected to have significantly improved high‐power and high‐temperature performance due to its ultrawide bandgap of close to 5 eV. However, the high‐temperature operation of these ultrawide‐bandgap devices is usually limited by the relatively low 1–2 eV built‐in potential at the Schottky barrier with most high‐work‐function metals. Herein, heterojunction p ‐NiO/n‐ β ‐Ga 2 O 3 diodes fabrication and optimization for high‐temperature device applications are reported, demonstrating a current rectification ratio ( I ON / I OFF ) of more than 10 6 at 410 °C. The NiO heterojunction diode can achieve higher turn‐on ( V ON ) voltage and lower reverse leakage current compared to the Ni‐based Schottky diode fabricated on the same single‐crystal β ‐Ga 2 O 3 substrate, despite charge transport dominated by interfacial recombination. Electrical characterization and device modeling show that these advantages are due to a higher built‐in potential and additional band offset. These results suggest that heterojunction p–n diodes based on β ‐Ga 2 O 3 can significantly improve high‐temperature electronic device and sensor performance.

Sohel, Shahadat H.↗

Thermal Management for Planar Package Power Electronics (CRADA Final Report)

The National Renewable Energy Laboratory (NREL) and John Deere Electronic Solutions (JDES) collaborated to develop and evaluate computer models and simulations related to the thermal performance of semiconductor device packaging for an inverter of an off-road vehicle ("Semiconductor Packaging"). The objective of the research was for NREL and JDES to develop a two or three-dimensional computer-aided design model of the Semiconductor Packaging ("Computer Model") for thermal performance evaluation in a simulation. The project developed computer models of a Semiconductor Package of silicon-carbide semiconductor devices with appropriate thermal dissipation via one or more of the following thermal features: a double-sided planar cooling configuration, an air-cooled configuration, a liquid-cooled configuration for off-road inverter applications in a relevant simulated operating environment. It is noted that surface area and prototype product embodiment consisting of air-cooled and liquid-cooled configurations may and may not be in direct contact with power semiconductor chips. The idea was to explore and develop packaging and thermal management technology for power semiconductors that was most effective in the performance yet had least burden in overall product cost for a given application.

33 ADVANCED PROPULSION SYSTEMS↗

N-type molecular doping of a semicrystalline conjugated polymer through cation exchange

Control of electrical doping is indispensable in any semiconductor device, and both efficient hole and electron doping are required for many devices. In organic semiconductors, however, electron doping has been essentially more problematic compared to hole doping because in general organic semiconductors have low electron affinities and require dopants with low ionization potentials that are often air-sensitive. Here, we adapt an efficient molecular doping method, so-called ion-exchange doping, to dope electrons in a polymeric semiconductor. We initially reduce the polymeric semiconductor using one electron transfer from molecular dopants, and then the ionized dopants in the resulting air-unstable films are replaced with secondary ions via cation exchange. Improved ambient stability and crystallinity of the doped polymeric semiconductors are achieved when a specific bulky molecular cation was chosen as the secondary ion, compared to conventional methods. The presented strategy can overcome the trade-off relationship between reducing capability and ambient stability in molecular dopants, and a wider selection of dopant ions will help to realize ambient-stable electron conductors.

36 MATERIALS SCIENCE↗

Evaluation of Converter Performance Considering Static and Dynamic Device Part-to-Part Variability

This paper presents a methodology to incorporate and analyze the impact of semiconductor device part-to-part variation on power converter performance. By integrating extensive static and dynamic device characterization data with an automated compact model generation process that reflects manufacturing variability, device models with inherent variability features are utilized in converter simulations for a comprehensive assessment of performance impacts. The traditional converter performance evaluation process typically yields fixed efficiency values, often dismissing the inherent part-to-part variability caused by the manufacturing process of semiconductor devices. To address this limitation, a large population of devices was characterized to capture variations in static parameters-such as transfer, output, and capacitance characteristics-as well as dynamic behaviors, including switching losses. This data-driven approach enables the development of individual compact models, which were then integrated into converter simulations to evaluate efficiency ranges rather than single point estimated values. The converter simulation results show that part-to-part component variation can lead to significant efficiency deviations, exceeding several percentage points in high-power conversion applications. By offering a more accurate representation of converter behavior under real-world manufacturing conditions, this methodology enables designers to anticipate performance variability, improving the robustness of power converter designs.

device characterization↗

PowerAmerica (Final Technical Report)

The U.S. Department of Energy’s Advanced Manufacturing Office (predecessor to AMMTO) established PowerAmerica in December 2014 to develop and accelerate the adoption of wide bandgap (WBG) semiconductor chips and power electronics in manufacturing. The objective was to spark early commercialization of energy efficient products; educate and train the workforce; create high-tech jobs; and nurture the growth of the U.S. WBG semiconductor manufacturing industry. PowerAmerica isled by North Carolina State University by way of a five-year, $140M cooperative agreement with DoE. This private-public partnership with DoE includes member companies ranging from startups and small-medium enterprises to large system integrators, world-class universities, and national labs. The WBG power electronic ecosystem formed by our diverse membership is focused on using advanced manufacturing to 1) lower the cost of silicon carbide and gallium nitride semiconductor devices to be comparable to silicon devices; 2) demonstrate the system benefits and energy efficiency advantages of WBG semiconductor power electronics through system demonstrations that validate their effectiveness; and 3) build an education pipeline for a skilled workforce to meet the future demand for emerging WBG semiconductor markets — and enhance U.S. economic competitiveness globally. PowerAmerica was initially funded in six budget periods, each lasting 12 to 18 months. By the end of Budget Period 6 (August 2023), PowerAmerica had achieved its major objectives in technology development, semiconductor device cost reduction, ecosystem growth and engagement, and education and workforce development. Through strategic foundry investments, we helped to establish the first U.S. SiC foundry (X-FAB) and supported a lab (Microchip) to start SiC volume production. We’ve helped bring together companies from different parts of the supply chain, resulting in several successful new partnerships and business relationships. Through projects with some of the largest manufacturers of energy-intensive equipment in the U.S. — John Deere, GE, United Technologies, Raytheon, Carrier, Toshiba, and others — we have successfully demonstrated the energy and system benefits of WBG technology. We have also harnessed the unique capabilities and facilities of national labs — the Naval Research Laboratory, National Renewable Energy Laboratory, and Argonne National Laboratory — to help solve challenging technical problems for industry. Thanks to our many webinars, tutorials, annual events, and presence at major energy and electronics conferences around the world, the PowerAmerica name has become synonymous with WBG technology advancement. The commercial interest in WBG technology is higher than ever; companies and governments around the world have announced hundreds of millions of dollarsin future investment to build capacity — and compete with silicon in many markets and applications. We have trained hundreds of engineering students, from universities across the U.S., through hands-on projects and WBG coursework. Working professionals have also benefited through the years from our many targeted short courses, tutorials, and technical webinars. In short, PowerAmerica has made great strides in each of our key objectives, and the organization has been operating without government or NC State

14 SOLAR ENERGY↗

Low temperature recovery of OFF-state stress induced degradation of AlGaN/GaN high electron mobility transistors

Thermal annealing is a widely used strategy to enhance semiconductor device performance. However, the process is complex for multi-material multi-layered semiconductor devices, where thermoelastic stresses from lattice constant and thermal expansion coefficient mismatch may create more defects than those annealed. We propose an alternate low temperature annealing technique, which utilizes the electron wind force (EWF) induced by small duty cycle high density pulsed current. To demonstrate its effectiveness, we intentionally degrade AlGaN/GaN high electron mobility transistors (HEMTs) with accelerated OFF-state stressing to increase ON-resistance ∼182.08% and reduce drain saturation current ∼85.82% of pristine condition at a gate voltage of 0 V. We then performed the EWF annealing to recover the corresponding values back to ∼122.21% and ∼93.10%, respectively. The peak transconductance, degraded to ∼76.58% of pristine at the drain voltage of 3 V, was also recovered back to ∼92.38%. This recovery of previously degraded transport properties is attributed to approximately 80% recovery of carrier mobility, which occurs during EWF annealing. We performed synchrotron differential aperture x-ray microscopy measurements to correlate these annealing effects with the lattice structural changes. We found a reduction of lattice plane spacing of (001) planes and stress within the GaN layer under the gate region after EWF annealing, suggesting a corresponding decrease in defect density. Application of this low-temperature annealing technique for in-operando recovery of degraded electronic devices is discussed.

Physics↗

Role of Decomposition Product Ions in Hysteretic Behavior of Metal Halide Perovskite

Ion migration is one of the most debated mechanisms and credited with multiple observed phenomena and performance in metal halide perovskites (MHPs) semiconductor devices. However, to date, the migration of ions and their effects on MHPs are not still fully understood, largely due to a lack of direct observations of temporal ion migration. In this work, using direct observation of ion migration in-operando, we observe the hysteretic migration behavior of intrinsic ions (i.e., CH 3 NH 3 + and I – ) as well as reveal the migration behavior of CH 3 NH 3 + decomposition ions. We find that CH 3 NH 3 + decomposition products can be affected by light and accumulate at the interfaces under bias. These MHP decomposition products are tightly related to the device performance and stability. Complementary results of time-resolved Kelvin probe force microscopy (tr-KPFM) demonstrate a correlation between dynamics of these interfacial ions and charge carriers. Overall, we find that there are a number of mobile ions including CH 3 NH 3 + decomposition products in MHPs that need to be taken into account when measuring MHP device responses (e.g., charge dynamics) and should be considered in future optimization studies of MHP semiconductor devices.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Directly Linking Low-Angle Grain Boundary Misorientation to Device Functionality for GaAs Grown on Flexible Metal Substrates

A new growth method to make highly oriented GaAs thin films on flexible metal substrates has been developed, enabling roll-to-roll manufacturing of flexible semiconductor devices. The grains are oriented in the <001> direction with <1 degree misorientations between them, and they have a comparable mobility to single-crystalline GaAs at high doping concentrations. At the moment, the role of low-angle grain boundaries (LAGBs) on device performance is unknown. A series of electron backscatter diffraction (EBSD) and cathodoluminesence (CL) studies reveal that increased doping concentrations decrease the grain size and increase the LAGB misorientation. Cross-sectional scanning transmission electron microscopy (STEM) reveals the complex dislocation structures within LAGBs. Most importantly, a correlative EBSD/electron beam-induced current (EBIC) experiment reveals that LAGBs are carrier recombination centers and that the magnitude of recombination is dependent on the degree of misorientation. The presented results directly link increased LAGB misorientation to degraded device performance, and therefore, strategies to reduce LAGB misorientations and densities would improve highly oriented semiconductor devices.

36 MATERIALS SCIENCE↗

Spin-helical detection in a semiconductor quantum device with ferromagnetic contacts

Spin-helical states, which arise in quasi-one-dimensional (1D) channels with spin-orbital (SO) coupling, underpin efforts to realize topologically protected quantum bits based on Majorana modes in semiconductor nanowires. Detecting helical states is challenging due to non-idealities present in real devices. Past efforts have focused on devices with normal contacts. In contrast, here we show by means of tight-binding calculations that by using ferromagnetic contacts it is possible to detect helical modes with high sensitivity even in the presence of realistic device effects, such as quantum interference. We show that by taking advantage of the spin-selective transmission properties of helical states, new transport signatures become possible. In addition, we show that spin-polarized contacts provide a unique path to investigate the spin-texture and spin-momentum locking properties of helical states. Our results are of interest not only for the ongoing development of Majorana qubits, but also for realizing possible spin-based quantum devices, such as quantum spin modulators and interconnects based on spin-helical channels.

36 MATERIALS SCIENCE↗

Charge carrier motion and effect of fixed oxide charge in a microstructured silicon radiation detector

Signal formation in a microstructured semiconductor neutron detector is more complex than in planar diode geometry. Three-dimensional microstructures are laterally smaller than the ionization cloud length, and the electric fields may be weak enough to exhibit plasma time effects. This work is the first detailed treatment of charge carrier motion in these complex semiconductor devices to replicate the time profile and signal magnitude. Simulations were performed using COMSOL Multiphysics to investigate various parameters that affect the propagation of the charge cloud. It was observed that the size of the simulated three-dimensional structure had an impact on the induced current pulse, indicating the importance of simulation geometry optimization to accurately simulate charge cloud expansion. COMSOL Multiphysics was used to replicate accurate charge creation profiles using energy deposition information imported from radiation transport codes. A detailed simulation methodology is presented to benchmark preamplifier event pulses along with complexities in modeling the charge carrier motion along the etched microstructured trenches with Si–SiO 2 boundary conditions, including fixed oxide charge and interface trapping.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Sandia National Laboratories FY20 Progress Report

The Energetic Neutrons campaign led by Sandia National Laboratories (SNL) had a successful year testing electronic devices and printed circuit boards (PCBs) under 14 MeV neutron irradiation at OMEGA. During FY20 the Energetic Neutrons campaign increased the number and complexity of experiments, continued collaborations with external organizations, and generated knowledge that supports SNL’s National Security mission. In FY20 the Energetic Neutrons campaign was executed by an early career team led by a new PI. The SNL team members were trained to take over new responsibilities during the shot day to increase the number and complexity of experiments in the campaigns. Also, in FY20 for the first time the Energetic Neutrons campaign had a graduate student contributing with pre and post-irradiation characterizations at SNL of the semiconductor devices irradiated at OMEGA. In FY20 SNL collaborated with the Air Force Nuclear Weapons Center (AFNWC) and supported experiments related to radiation effects in semiconductor devices. SNL also gave the opportunity to ride along to Los Alamos National Laboratory and multiple scientists from MIT and LLE. SNL continued using the last two generations of the Neutron Effects Diagnostics (NEDs) to field active and passive experiments but also redesigned the latest generation of the NEDs to accommodate larger components and improve the vacuum sealing as shown in figure 1a. The redesigned NEDs allowed SNL to perform active tests of a high voltage (HV) PCB for the first time at OMEGA; where signals before, during and after the irradiation were recorded. The HV PCB installed in one of the SNL NEDs is shown in figure 1b where a 3D-printed nosecone was used to check for mechanical and electrical interference. Passive irradiations of multiple components were followed up with leakage current, gain measurements and radiation-induced defect characterization.

42 ENGINEERING↗

A fast implicit solver for semiconductor models in one space dimension

Several different approaches are proposed for solving fully implicit discretizations of a simplified Boltzmann-Poisson system with a linear relaxation-type collision kernel. This system models the evolution of free electrons in semiconductor devices under a low-density assumption. At each implicit time step, the discretized system is formulated as a fixed-point problem, which can then be solved with a variety of methods. A key algorithmic component in all the approaches considered here is a recently developed sweeping algorithm for Vlasov-Poisson systems. A synthetic acceleration scheme has been implemented to accelerate the convergence of iterative solvers by using the solution to a drift-diffusion equation as a preconditioner. The performance of four iterative solvers and their accelerated variants has been compared on problems modeling semiconductor devices with various electron mean-free-path.

97 MATHEMATICS AND COMPUTING↗

Metal oxide semiconductor (MOS) controlled devices and methods of making the same

Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.

36 MATERIALS SCIENCE↗

Metal oxide semiconductor (MOS) controlled devices and methods of making the same

Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device.The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.

Matocha, Kevin↗

Area-selective deposition of germanium on patterned graphene/monolayer molybdenum disulfide stacks via dipole engineering

Heterogeneous integration of two-dimensional materials and the conventional semiconductor has opened opportunities for next-generation semiconductor devices and their processing. Heterogeneous integration has been studied for economical manufacturing by substrate recycling and novel functionalities by a combination of incommensurate materials. However, utilizing the integration requires controlling locations of the integrated architectures. Here, we show area-selective deposition (ASD) of germanium on the graphene/MoS 2 stack. Ge nucleation precisely occurred on the surfaces of the patterned graphene/MoS 2 stack via dipole engineering. In this study, the growth temperature of ASD of Ge was significantly lower than that based on precursor desorption on SiO 2 . The first-principles calculations revealed that Ge deposited by ASD on the graphene/MoS 2 stack was not affected by charge transfer. This work provides a viable way to utilize atomically thin materials for next-generation semiconductor devices, which can be applicable for “Beyond Moore” and “More Moore” approaches.

2D materials↗

Mechanical Properties of 2D LiInP 2 Se 6 : Implication for Semiconductor Applications

Metal phosphorus trichalcogenides (MPTCs) are emerging 2D semiconductor materials with unique functional properties that set them apart from other 2D systems. Despite the importance of their mechanical properties for improving the semiconductor device’s durability and performance, as well as for utilizing strain effects to customize material properties and create new functionality, our current understanding of MPTCs’ mechanical behavior is lacking and lags behind our knowledge of their other properties. Here, we use LiInP 2 Se 6 as a model example of MPTCs and report the first experimental measurements of the elastic and plastic (fracture) properties along both in-plane and out-of-plane directions by atomic force microscopy and nanoindentation. Being a 2D material that is entirely inorganic, LiInP 2 Se 6 surprisingly exhibits mechanical properties that resemble those of hybrid organic–inorganic materials rather than pure inorganic 2D materials. It has a soft crystal structure with low elastic moduli, a low difference in in-plane vs out-of-plane mechanical properties, and a combination of elastic and plastic characteristics of hybrid organic–inorganic materials. Furthermore, our work provides the mechanical information critically needed to mitigate and/or harness the strain effects in LiInP 2 Se 6 -based semiconductor devices and sheds light on the mechanical behaviors of MPTCs with indispensable insights.

2D semiconductor↗