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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

A Novel Resilience-Oriented Cellular Grid Formation Approach for Distribution Systems with Behind-the-Meter Distributed Energy Resources

This paper presents a resilience-oriented cellular grid formation approach to achieve scalable and reconfigurable community microgrid operations for distribution systems with behind-the-meter distributed energy resources. A set of interconnected solar photovoltaics, energy storage systems, and load is termed as a cell, implying a subset of the grid that can operate independently using its own resources. Cells are identified such that each cell inherently has sufficient energy resources to black start and can provide a certain level of backup power for its load under the loss of utility power supply. The proposed cell formation approach builds on a unique self-organizing map-based method (SomRes) to quantify a system's resilience. Using SomRes and a non-dominated sorting-based genetic algorithm (NSGA-II), a fast and efficient cell formation algorithm is developed to identify cells in a distribution system that are resilient against extreme events. The efficacy of the proposed approach is demonstrated on a numerical model of a real distribution feeder in Colorado, United States.

distributed energy resource↗
NASA NTRS2006

TRIGA: Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays

We present the Telecommunications protocol processing subsystem using Reconfigurable Interoperable Gate Arrays (TRIGA), a novel approach that unifies fault tolerance, error correction coding and interplanetary communication protocol off-loading to implement CCSDS File Delivery Protocol and Datalink layers. The new reconfigurable architecture offers more than one order of magnitude throughput increase while reducing footprint requirements in memory, command and data handling processor utilization, communication system interconnects and power consumption.

protocol processing hardware engine↗
NASA NTRS2014

Space-Based Reconfigurable Software Defined Radio Test Bed Aboard International Space Station

The National Aeronautical and Space Administration (NASA) recently launched a new software defined radio research test bed to the International Space Station. The test bed, sponsored by the Space Communications and Navigation (SCaN) Office within NASA is referred to as the SCaN Testbed. The SCaN Testbed is a highly capable communications system, composed of three software defined radios, integrated into a flight system, and mounted to the truss of the International Space Station. Software defined radios offer the future promise of in-flight reconfigurability, autonomy, and eventually cognitive operation. The adoption of software defined radios offers space missions a new way to develop and operate space transceivers for communications and navigation. Reconfigurable or software defined radios with communications and navigation functions implemented in software or VHDL (Very High Speed Hardware Description Language) provide the capability to change the functionality of the radio during development or after launch. The ability to change the operating characteristics of a radio through software once deployed to space offers the flexibility to adapt to new science opportunities, recover from anomalies within the science payload or communication system, and potentially reduce development cost and risk by adapting generic space platforms to meet specific mission requirements. The software defined radios on the SCaN Testbed are each compliant to NASA's Space Telecommunications Radio System (STRS) Architecture. The STRS Architecture is an open, non-proprietary architecture that defines interfaces for the connections between radio components. It provides an operating environment to abstract the communication waveform application from the underlying platform specific hardware such as digital-to-analog converters, analog-to-digital converters, oscillators, RF attenuators, automatic gain control circuits, FPGAs, general-purpose processors, etc. and the interconnections among different radio components.

Communications↗
DOE OSTI2025

Structured liquid-based reconfigurable all-liquid optical fibers

Quartz optical fibers are brittle, difficult to repair, and lack reconfigurability, limiting their adaptability in underwater communication. To overcome these impediments, here we show reconfigurable all-liquid optical fibers (RAOFs) produced by structured liquid, tuned by the interfacial assembly and jamming of nanoparticle surfactants at the water-oil interface (interfacial tension <10 mN m -1 , refractive index contrast of 0.083). These RAOFs combine the structural stability of the interfacial assemblies with the inherent flexibility of liquids. They support real-time communication on an Ethernet platform (up to 1 Gbps), providing a practical alternative to conventional optical fibers for optical interconnects. Their liquid nature enables broken fibers to be repaired rapidly by a coalescence process. Their softness affords on-demand reconfigurability that enables in-situ fabrication of reconfigurable optical fibers and dynamic manipulation of signal transmission. RAOFs provide a versatile, self-healing, and resilient solution for optical communication systems in dynamic environments.

Zhao, Sai [City University of Hong Kong, Kowloon (↗
NASA NTRS1989

Fault tolerant hypercube computer system architecture

A fault-tolerant multiprocessor computer system of the hypercube type comprising a hierarchy of computers of like kind which can be functionally substituted for one another as necessary is disclosed. Communication between the working nodes is via one communications network while communications between the working nodes and watch dog nodes and load balancing nodes higher in the structure is via another communications network separate from the first. A typical branch of the hierarchy reporting to a master node or host computer comprises, a plurality of first computing nodes; a first network of message conducting paths for interconnecting the first computing nodes as a hypercube. The first network provides a path for message transfer between the first computing nodes; a first watch dog node; and a second network of message connecting paths for connecting the first computing nodes to the first watch dog node independent from the first network, the second network provides an independent path for test message and reconfiguration affecting transfers between the first computing nodes and the first switch watch dog node. There is additionally, a plurality of second computing nodes; a third network of message conducting paths for interconnecting the second computing nodes as a hypercube. The third network provides a path for message transfer between the second computing nodes; a fourth network of message conducting paths for connecting the second computing nodes to the first watch dog node independent from the third network. The fourth network provides an independent path for test message and reconfiguration affecting transfers between the second computing nodes and the first watch dog node; and a first multiplexer disposed between the first watch dog node and the second and fourth networks for allowing the first watch dog node to selectively communicate with individual ones of the computing nodes through the second and fourth networks; as well as, a second watch dog node operably connected to the first multiplexer whereby the second watch dog node can selectively communicate with individual ones of the computing nodes through the second and fourth networks. The branch is completed by a first load balancing node; and a second multiplexer connected between the first load balancing node and the first and second watch dog nodes, allowing the first load balancing node to selectively communicate with the first and second watch dog nodes.

Madan, Herb S.↗
NASA NTRS1993

High-performance mass storage system for workstations

Reduced Instruction Set Computer (RISC) workstations and Personnel Computers (PC) are very popular tools for office automation, command and control, scientific analysis, database management, and many other applications. However, when using Input/Output (I/O) intensive applications, the RISC workstations and PC's are often overburdened with the tasks of collecting, staging, storing, and distributing data. Also, by using standard high-performance peripherals and storage devices, the I/O function can still be a common bottleneck process. Therefore, the high-performance mass storage system, developed by Loral AeroSys' Independent Research and Development (IR&D) engineers, can offload a RISC workstation of I/O related functions and provide high-performance I/O functions and external interfaces. The high-performance mass storage system has the capabilities to ingest high-speed real-time data, perform signal or image processing, and stage, archive, and distribute the data. This mass storage system uses a hierarchical storage structure, thus reducing the total data storage cost, while maintaining high-I/O performance. The high-performance mass storage system is a network of low-cost parallel processors and storage devices. The nodes in the network have special I/O functions such as: SCSI controller, Ethernet controller, gateway controller, RS232 controller, IEEE488 controller, and digital/analog converter. The nodes are interconnected through high-speed direct memory access links to form a network. The topology of the network is easily reconfigurable to maximize system throughput for various applications. This high-performance mass storage system takes advantage of a 'busless' architecture for maximum expandability. The mass storage system consists of magnetic disks, a WORM optical disk jukebox, and an 8mm helical scan tape to form a hierarchical storage structure. Commonly used files are kept in the magnetic disk for fast retrieval. The optical disks are used as archive media, and the tapes are used as backup media. The storage system is managed by the IEEE mass storage reference model-based UniTree software package. UniTree software will keep track of all files in the system, will automatically migrate the lesser used files to archive media, and will stage the files when needed by the system. The user can access the files without knowledge of their physical location. The high-performance mass storage system developed by Loral AeroSys will significantly boost the system I/O performance and reduce the overall data storage cost. This storage system provides a highly flexible and cost-effective architecture for a variety of applications (e.g., realtime data acquisition with a signal and image processing requirement, long-term data archiving and distribution, and image analysis and enhancement).

Chiang, T.↗
DOE OSTI2024

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1987

Programming methodology for a general purpose automation controller

The General Purpose Automation Controller is a multi-processor architecture for automation programming. A methodology has been developed whose aim is to simplify the task of programming distributed real-time systems for users in research or manufacturing. Programs are built by configuring function blocks (low-level computations) into processes using data flow principles. These processes are activated through the verb mechanism. Verbs are divided into two classes: those which support devices, such as robot joint servos, and those which perform actions on devices, such as motion control. This programming methodology was developed in order to achieve the following goals: (1) specifications for real-time programs which are to a high degree independent of hardware considerations such as processor, bus, and interconnect technology; (2) a component approach to software, so that software required to support new devices and technologies can be integrated by reconfiguring existing building blocks; (3) resistance to error and ease of debugging; and (4) a powerful command language interface.

Sturzenbecker, M. C.↗
DOE OSTI2023

Multi-Port Autonomous Reconfigurable Solar Power Plant

As the penetration level of power electronics increases and remote photovoltaic (PV) generation is integrated into the alternating current (ac) grid, the short-circuit ratio (SCR) at the point of interconnection of a hybrid PV–energy storage system (ESS) plant may be low. Additionally, the inertia of the alternating current (ac) grid may be low. The low SCRs and inertias can lead to reliability challenges in the power grid. These operating conditions require additional reinforcements, such as synchronous condensers, static var compensators, static synchronous compensators, and high-voltage direct current (HVdc) links/grids. HVdc links or grids may also provide the additional capability of connecting the plant to asynchronous grids and/or connecting asynchronous grids, among others. This scenario leads to discrete development of solar inverters, energy storage inverters, HVdc converters, and several transformers. Some of the problems associated with this discrete development and inverter-based generation include increased cost, lower reliability, and reduced efficiency associated with duplication of power electronics (PEs); competing controls of several individual discrete inverter-based generators due to the presence of multiple PEs, which leads to derating of the system; and transient stability problems arising from inverter-based generation, such as voltage/frequency events leading inverter shutdowns, voltage instability and control interactions in the formed weak grid, and harmonics caused by resonances of multiple inverters.

14 SOLAR ENERGY↗
DOE OSTI2023

A review of crosstalk polymorphic circuits and their scalability

Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1993

Design for an integrated discipline operations control center for Space Station Freedom

This paper presents selected features of a human factors oriented plan for a Space Station Freedom (SSF) ground Discipline Operations Center (DOC) that is integrated with other work areas used by multidisciplinary life scientists. This combined facility is referred to as an integrated DOC or IDOC. This plan is based upon the assumption that there will be a constantly changing array of specialized equipment and procedures used by life sciences principal investigators (PI) on the ground which must be linked to SSF through various DOC systems. Other sites will also be able to communicate with SSF (Anon., 1992). It is also assumed that cost reduction will be a major design consideration and that one integrated structure will be less expensive to build and operate than two separate ones. Since both the DOC personnel and PIs will need to communicate with the flight crew aboard SSF, the general interconnect architecture of the PIs' communication linkage is considered here. Key human factor design elements of this plan include: a candidate facility layout which accommodates three (3), multipurpose, rapidly reconfigurable work areas (suites) and consequent user traffic flow considerations, a multimedia telecommunications support capability, functional (human) traffic flow, optimized internal illumination and acoustics requirements, selected volumetric and safety requirements, and other architectural design parameters.

Haines, Richard F.↗
DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
NASA NTRS2015

Standardized Modular Power Interfaces for Future Space Explorations Missions

Earlier studies show that future human explorations missions are composed of multi-vehicle assemblies with interconnected electric power systems. Some vehicles are often intended to serve as flexible multi-purpose or multi-mission platforms. This drives the need for power architectures that can be reconfigured to support this level of flexibility. Power system developmental costs can be reduced, program wide, by utilizing a common set of modular building blocks. Further, there are mission operational and logistics cost benefits of using a common set of modular spares. These benefits are the goals of the Advanced Exploration Systems (AES) Modular Power System (AMPS) project. A common set of modular blocks requires a substantial level of standardization in terms of the Electrical, Data System, and Mechanical interfaces. The AMPS project is developing a set of proposed interface standards that will provide useful guidance for modular hardware developers but not needlessly constrain technology options, or limit future growth in capability. In 2015 the AMPS project focused on standardizing the interfaces between the elements of spacecraft power distribution and energy storage. The development of the modular power standard starts with establishing mission assumptions and ground rules to define design application space. The standards are defined in terms of AMPS objectives including Commonality, Reliability-Availability, Flexibility-Configurability and Supportability-Reusability. The proposed standards are aimed at assembly and sub-assembly level building blocks. AMPS plans to adopt existing standards for spacecraft command and data, software, network interfaces, and electrical power interfaces where applicable. Other standards including structural encapsulation, heat transfer, and fluid transfer, are governed by launch and spacecraft environments and bound by practical limitations of weight and volume. Developing these mechanical interface standards is more difficult but an essential part of defining physical building blocks of modular power. This presentation describes the AMPS projects progress towards standardized modular power interfaces.

Spacecraft Power↗
NASA NTRS1988

Space Station power system autonomy demonstration

The Systems Autonomy Demonstration Program (SADP) represents NASA's major effort to demonstrate, through a series of complex ground experiments, the application and benefits of applying advanced automation technologies to the Space Station project. Lewis Research Center (LeRC) and Marshall Space Flight Center (MSFC) will first jointly develop an autonomous power system using existing Space Station testbed facilities at each center. The subsequent 1990 power-thermal demonstration will then involve the cooperative operation of the LeRC/MSFC power system with the Johnson Space Center (JSC's) thermal control and DMS/OMS testbed facilities. The testbeds and expert systems at each of the NASA centers will be interconnected via communication links. The appropriate knowledge-based technology will be developed for each testbed and applied to problems requiring intersystem cooperation. Primary emphasis will be focused on failure detection and classification, system reconfiguration, planning and scheduling of electrical power resources, and integration of knowledge-based and conventional control system software into the design and operation of Space Station testbeds.

Kish, James A.↗
DOE OSTI2026

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗
NASA NTRS1994

Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors

In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

Fijany, Amir↗
NASA NTRSDate not supplied

Autonomous In-space Construction, Maintenance, and Reconfiguration Using Programmable Meta-Material

NASA ARC's Coded Structures Laboratory (CSL) is developing autonomous construction, maintenance, and reconfiguration technologies to meet long-duration and deep space infrastructure needs, in accordance with long-term NASA goals of "in-space reliance" and "mass-less exploration." We seek to achieve these capabilities by utilizing a "programmable meta-material" approach that integrates emerging advances in materials (mechanical meta-materials), manufacturing (cooperative mobile robotics), and autonomy (multi-agent planning algorithms). Through the ARMADAS project, we have shown assembly of high-performance engineered cellular materials using multiple cooperating mobile robotic assemblers. In this paper, we describe how such a programmable meta-material architecture may shift the paradigm of how we design, build, manufacture, and operate future space infrastructure and assets. The core of a programmable meta-material architecture consists of 3 main technology sub-areas: the structure, the assembly agents, and the assembly algorithms. We co-design these systems to ensure an adaptable system that can create and reconfigure structures from a base set of building block components. From this core technology, we can branch out and expand the capability of the system through additional secondary component types and robotic agents to perform activities such as inspections, maintenance, repair, payload installation, or perform power and communications interconnect. As these technologies mature, future designers will be able to utilize the system to rapidly integrate and operate assets in space or on planetary surfaces from a set of well-tested part library, or create their own modules to integrate into the system. A core trait to the development of this system is the automation approach. Because of the modular and functional discrete (pixel-like) nature of the structural system, a diverse set of powerful algorithms for analysis, planning, and simulation can be adapted and leveraged to optimize construction, maintenance, and dynamic reorganization (as hardware with programmable form and function). With an ability to free the design space from launch vehicle constraints and fundamentally shift how a mission is designed and conducted, we discuss the influence of a programmable meta-material architecture on mission design, build, and operations. For the "design phase", we discuss project lifecycle effects, costs, time, and performance. For the "build phase", we discuss reusability, ISRU, manufacturing, material logistics, and scalability. And for "operations", we discuss autonomy, maintenance and upgrades, reliability, and reconfiguration. Autonomy and modularity are the primary enabling traits of this system. Engineering systems that utilize a modular and reconfiguration building block approach such as digital communication and computation systems, currently lead all other areas of technology in size and complexity scalability. NASA is extending the benefits and flexibility of digital systems to hardware systems, to optimize materials lifecycle management and expand our space exploration mission capabilities.

in space assembly↗
DOE OSTI2025

Magnetic Solitons and Thickness‐Dependent Magnetization Reversal in Interconnected Helical Nanowire Arrays

By expanding magnetic nanostructures into the third dimension, it is possible to introduce new interactions and realize new forms of magnetic textures and emergent phenomena. Consequently, this unlocks new opportunities for applications in data storage, unconventional computing and sensing by utilizing 3D devices with enhanced functionalities. Connected magnetic nanowires offer a unique platform for applications such as neuromorphic computing due to their tunability and the presence of multiple transport pathways. However to realize this promise, it is necessary to further our understanding of how to locally control the magnetization in 3D, nanowire-based geometries. In this work we show the formation of magnetic domain walls, vortices, anti-vortices, and linked vortex-anti-vortex pairs in interconnected helical nanowire arrays. We show how wire diameter and 3D geometric design can control the states that form and reveal the magnetization reversal mechanism. Hence, we demonstrate this to be a highly tunable system, where the magnetization can be readily reconfigured by an external magnetic field.

3D Nanomagnetism↗